• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.281-284
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• 2001

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.

• Journal of Advanced Marine Engineering and Technology
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• 제25권6호
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• pp.1353-1361
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• 2001

Vortex lock-on or resonance behind a circular cylinder is visualized using a time-resolved PW when a single frequency oscillation is superimposed on the mean incident velocity. For vector processing, a cross-correlation algorithm in conjunction with a recursive correlation and interrogation window shifting techniques is used. Measurements are made of the Karmas and streamwise vertices in the wake-transition regime at Reynolds lumber 360. When lock-on occurs, the vortex shedding frequency is found to be half the oscillation frequency as expected from previous experiments. At the lock-on state, the Karman vortices are observed to be more disordered by the increased strength and spanwise wavelength of the streamwiee vortices, which lead? to a strong three-dimensional motion.

• 한국전산유체공학회지
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• 제6권4호
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• pp.26-34
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• 2001

The flow past a circular cylinder forced to vibrate transversely is numerically simulated by solving the two-dimensional Navier-Stokes equations modified by the vibration velocity of a circular cylinder at a Reynolds number of 164. The higher-order finite difference scheme is employed for the spatial discretization along with the second order Adams-Bashforth and the first order backward-Euler time integration. The calculated cylinder vibration frequency is between 0.60 and 1.30 times of the natural vortex-shedding frequency. The calculated oscillation amplitude extends to 25% of the cylinder diameter and in the case of the lock-in region it is 60%. It is made clear that the cylinder oscillation has influence on the wake pattern, the time histories of the drag and lift forces, power spectral density and phase diagrams, etc. It is found that these results include both the periodic (lock-in) and the quasi-periodic (non-lock-in) state. The vortex shedding frequency equals the driving frequency in the lock-in region but is independent in the non-lock-in region. The mean drag and the maximum lift coefficient increase with the increase of the forcing amplitude in the lock-in state. The lock-in boundaries are also established from the present direct numerical simulation.

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2001년도 춘계 학술대회논문집
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• pp.181-188
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• 2001

The flow past a circular cylinder forced to vibrate transversely is numerically simulated by solving the two-dimensional Wavier-Stokes equations modified by the vibration velocity of a circular cylinder at a Reynolds number of 164. The higher-order finite difference scheme is employed for the spatial discretization along with the second order Adams-Bashforth and the first order backward-Euler time integration. The calculated cylinder vibration frequency is between 0.60 and 1.30 times of the natural vortex-shedding frequency. The calculated oscillation amplitude extends to $25\%$ of the cylinder diameter and in the case of the lock-in region it is $60\%$. It is made clear that the cylinder oscillation has influence on the wake pattern, the time histories of the drag and lift forces, power spectral density and phase diagrams, etc. It is found that these results include both the periodic (lock-in) and the quasi-periodic (non-lock-in) state. The vortex shedding frequency equals the driving frequency in the lock-in region but is independent in the non-lock-in region. The mean drag and the maximum lift coefficient increase with the increase of the forcing amplitude in the lock-in state. The lock-in boundaries are also established from the present direct numerical simulation.

• 한국가시화정보학회:학술대회논문집
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• 한국가시화정보학회 2001년도 Proceedings of 2001 Korea-Japan Joint Seminar on Particle Image Velocimetry
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• pp.86-99
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• 2001

Vortex lock-on or resonance in the flow behind a circular cylinder is investigated from a time-resolved PIV when a single frequency oscillation is superimposed on the mean incident velocity. Measurements are made of the $K\acute{a}rm\acute{a}n$ and streamwise vortices in the wake-transition regime at the Reynolds number 360. Streamwise vortices at the lock-on and natural shedding states are observed, as well as the changes in the wake region with the change of the shedding frequency of lock-on state. When lock-on occurs, the vortex shedding frequency is found to be half the oscillation frequency as expected from previous experiments. At the lock-on state, the $K\acute{a}rm\acute{a}n$ vortices are observed to be more disordered by the increased strength and spanwise wavelength of the streamwise vortices, which leads to a strong three-dimensional motion. Recirculation and vortex formation region at the lock-on state is reduced as the oscillating frequency is increased. By comparing the Reynolds stresses at the lock-on and natural shedding states, $\bar{u'u'}\;and \;\bar{u'u'}$ at the lock-on state are concentrated on the shear layer around the cylinder. The $\bar{u'u'}\;at\;f_o/f_n=2.0$ has a large value near the centerline, compared with that of other cases. Considering the traces of maximum of u', in the wake region near the cylinder, wake width at the lock-on state is wider than that at the natural shedding state.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1836-1840
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• 2003

This paper, we propose a new phase-locked loop (PLL) system with the controllable output phase, independent from the output frequency, and lock-up time. This PLL system has a dual control loop is described, the inner loop greatly improved VCO characteristic such as faster speed response as well as higher operation bandwidth, to minimize the effect of the VCO noise and the power supply variation and also get better linearity of VCO output. The main loop is the heart of this PLL which greatly improved the output frequency instability due to the external high frequency noise coupling to the input reference frequency also the main loop can control the output phase, independent from the output frequency, and reduce the lock-up time of the step frequency response. The experimental results confirm the validity of the proposed strategy.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권4호
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• pp.534-542
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• 2017

This paper presents a fast locking technique for a fractional-N PLL frequency synthesizer. The technique directly measures $K_{VCO}$ on a chip, computes the VCO's target tuning voltage for a given target frequency, and directly sets the loop filter voltage to the target voltage before the PLL begins the normal closed-loop locking process. The closed-loop lock time is significantly minimized because the initial frequency of the VCO are put very close to the desired final target value. The proposed technique is realized and designed for a 4.3-5.3 GHz fractional-N synthesizer in 65 nm CMOS and successfully verified through extensive simulations. The lock time is less than $12.8{\mu}s$ over the entire tuning range. Simulation verifications demonstrate that the proposed method is very effective in reducing the synthesizer lock time.

• 한국항공우주학회지
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• 제37권3호
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• pp.275-282
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• 2009

링레이저 자이로에는 입력각속도가 작은 영역에서 비선형적인 출력현상인 lock-in이 발생하는데 이를 제거하기 위하여 레이저 공진기에 정현파 각진동을 인가하는 방법이 주로 적용된다. 그러나, 그 방법을 적용하는 경우에도 각진동 회귀점에서 lock-in에 의한 오차가 남아있게 되는데, 이들 오차에 의하여 링레이저 자이로의 일반적인 오차특성인 랜덤웍이 발생된다. 이 lock-in에 의한 오차를 제거하기 위한 많은 연구결과 중의 한 방법으로써 lock-in오차 보상방법은 공진기 각진동 회귀점을 통과하기 전과 후의 맥놀이신호 주기를 비교하여 오차를 추정하고 보상하는 방법이다. 본 연구에서는 자이로 모델링 및 수치해석적인 방법으로, 이 lock-in오차 보상방법의 이론적인 적용 가능성을 분석하고, 현재 가능 할 것으로 판단되는 맥놀이 신호주기 측정 분해능을 감안하여 이 방법의 적용 효과를 분석하였다. 그 결과 lock-in오차 보상방법에 의하여 랜덤웍이 약 1/2~1/3로 감소될 수 있음을 알 수 있었다. 그러므로 이 방법은 항법장치의 정렬시간을 획기적으로 단축시킬 수 있는 방법이 될 것으로 기대된다.

• 한국정보통신학회논문지
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• 제10권9호
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• pp.1582-1589
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• 2006

잠금기법은 분산 병렬 시스템의 동기화에 필수적이다. 기존의 큐잉 잠금기법은 최초의 잠금 읽기와 잠금 경합발생 시 공유 데이터에 대한 잠금이 해제되었을 때 발생하는 잠금 읽기 재 시도로 두 개의 트래픽을 발생한다. 본 논문에서는 WPV(Waiting Processor Variable) 잠금기법이라 불리는 새로운 잠금기법을 제안한다 새로이 제안하는 기법은 오직 한 개의 잠금 읽기 명령을 사용한다. WPV 기법은 파이프라인 전송방식을 사용하여 최초의 잠금 읽기 단계에서 공유 데이터가 전송될 때까지 대기 한 후 잠금을 실시한다. 데이터에 대한 잠금을 수행중인 프로세서는 대기 상태의 다음 프로세서에 대한 정보를 저장하고 있으므로, 공유 데이터가 캐쉬 대 캐쉬 데이터 전송 기법에 의하여 대기중인 다음 프로세서로 바로 전송된다. 따라서 대기중인 프로세서 에 대한 변수는 연결 리스트 구조를 갖는다. 제안된 기법은 캐쉬 상태의 잠금기법을 사용하여 잠금 오버 헤드를 줄이고 다중 잠금 경합 발생시 FIFO를 유지하게 한다. 또한 본 논문에서는 기존의 메모리 및 캐쉬 큐잉 잠금기법에 대한 WPV 잠금기법의 해석적 모델링을 제시한다. WPV 잠금기법에 대한 시뮬레이션의 결과는 기존의 큐잉 잠금기법에 비하여 50%의 접근 시간의 감소를 보여주었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1201-1204
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• 2003

This paper described a replica-delay adaptive lock-acquisition scheme for high-speed DLLs. The proposed scheme provides the fast and correct locking cycle that is variable according to the magnitude of the arbitrary replica delay (fixed delay). The scheme guarantees the wide operation range and the fast lock-aquisition time. It has been confirmed by HSPICE simulations in a 0.35${\mu}{\textrm}{m}$ CMOS process.