• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1077-1087
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• 2003

In this paper, we proposed an architecture of a cryptosystem with various operating modes for the network security and implemented in hardware using the ASIC library. For configuring a cryptosystem, the standard block ciphers such as AES, SEED and 3DES were included. And the implemented cryptosystem can encrypt and decrypt the data in real time through the wired/wireless network with the minimum latency time (minimum 64 clocks, maximum 256 clocks). It can support CTR mode which is widely used recently as well as the conventional block cipher modes such as ECB, CBC and OFB, and operates in the multi-bit mode (64, 128, 192, and 256 bits). The implemented hardware has the expansion possibility for the other algorithms according to the network security protocol such as IPsec and the included ciphering blocks can be operated simultaneously. The self-ciphering mode and various ciphering mode can be supported by the hardware sharing and the programmable data-path. The global operation is programmed by the serial communication port and the operation is decided by the control signals decoded from the instruction by the host. The designed hardware using VHDL was synthesized with Hynix 0.25$\mu\textrm{m}$ CMOS technology and it used the about 100,000 gates. Also we could assure the stable operation in the timing simulation over 100㎒ using NC-verilog.

• Journal of Korean Physical Therapy Science
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• v.18 no.4
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• pp.31-46
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• 2011

The purpose of this survey was to give data and information about type and needs of Home Physical Therapy, Visiting Physical Therapy and School Physical Therapy for physical and nurse. The subjects were 154(99 physical therapists and 55 nurses) who were working at geriatric rehabilitation hospitals and children hospitals. The period of questionary collection was from the 15 of August to the 15th of September 2011. And data was analysis from 99 articles such as journals related to physical therapy, and searched with keyword 'home and visiting physical therapy' by web site and Korea National Assembly Library from 1991 to 2011. The data was analysis with percentage, mean, standard deviation and ANOVA by SPSS PC 12.0. The results were as follows; 1. The definition of 'Home Physical Therapy' has been community based on physical therapy service for the patient who had diagnosis by medical doctor, has been based on medical law. The definition of 'Visiting Physical Therapy' has been community based on physical therapy service at home for the patient who had diagnosis by medical doctor, for the national basic living security, and senior citizen over 65 years who lives alone, has been based on law for community health and law of long term health insurance. The definition of 'School Physical Therapy' has been school based on physical therapy service at school after class for the disabled children who are studying at school, has been based on special education law article 28. 2. As for the knowledge of the Home and Visiting and School Physical Therapy, both groups PT and nurse were 'I do not know'125(81.3%) of the difference the concept of 3 definitions, so it means to need education and information about the different concept of three physical therapy. As for the needs of home and visiting physical therapy, both groups of PT and Nurse were 'needs' 151(98.1%). Physical therapist showed of 'Needs' on visiting physical therapy 35(35.4%), home physical therapy 32(32.3%), and schole physical therapy 32(32.3%). Nurse showed of 'Needs' on home physical therapy 23(41.8%). visiting physical therapy 19(34.5%), school physical therapy 13(23.6%). Therefore it is necessary to have home and visiting physical therapy as for the elderly and disabled person. 3. As for the qualification of Home and Visiting physical therapist, both PT and nurse groups showed as follows; take post graduation education program for home and visiting therapy after became PT : home physical therapist 108(70.1%), visiting physical therapist 106(68.8%). So it means education center or university can be developed post graduation program for home and visiting physical therapist. 4. As for the 'Needs' of school physical therapy, both groups of PT and nurse showed as follows; 'Needs' 142(92.2%), 'Needs superviser education program' 148(96.1%), in PT group showed 'I will participate of education program' 92(92.9%). 5. As for the present states of research papers or report of home, visiting, and school physical therapy was as follows; the 103 papers for 8 fields about' the needs of home and visiting physical therapy' from 1991 to 2011, the 13 papers for 2 fields about school physical therapy from 2001 to 2011, so total papers were 114 articles.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.103-111
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• 2007

In this paper, we propose a VLSI architecture of hardware optimized high quality image signal processor for a Single-chip CMOS Image Sensor(CIS). The Single-chip CIS is usually used for mobile applications, so it has to be implemented as small as possible while maintaining the image quality. Several image processing algorithms are used in ISP to improve captured image quality. Among the several image processing blocks, demosaicing and image filter are the core blocks in ISP. These blocks need line memories, but the number of line memories is limited in a low cost Single-chip CIS. In our design, high quality edge-adaptive and cross channel correlation considered demosaicing algorithm is adopted. To minimize the number of required line memories for image filter, we share the line memories using the characteristics of demosaicing algorithm which consider the cross correlation. Based on the proposed method, we can achieve both high quality and low hardware complexity with a small number of line memories. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 37K, and seven and half line memories are used.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.102-111
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Motion Compensation in 4K UHD($3840{\times}2160$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $9{\times}9$ reference data for interpolation, we design 2D cache buffer which consists of the $9{\times}9$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The maximum operation frequency is 150MHz. The gate count is 161Kgates. The proposed H.264/AVC Motion Compensation can support 4K UHD at 72 frames per second by running at 150MHz.

• The Journal of Korean Academy of Sensory Integration
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• v.12 no.2
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• pp.25-36
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• 2014

Objective : The purpose of this study is learning the characteristics of literature applying single subject researches in the field of sensory integration therapy of Korean occupational therapy and evaluating the quality level of them. Methods : Analyzed the characteristics of 17 single subject research papers (independent variable, study design, study subject, total number of session, study period, intervention time, intervention place, dependent variable, measuring tool and result) published between 2002 and 2013 using the document delivery service of Korean Society of Occupational Therapy, National Discovery for Science Leaders (NDSL), Nuri Media (DBpia), Research Information Sharing Service (RISS), Korean Studies Information Service System (KISS) and National Assembly Library and evaluated the literatures using quality evaluation scale. Results : According to the analysis result on the literature characteristics, reversal design was the most used study method. Total number of session was 10 sessions to 34 sessions. Study period was 4 weeks to 16 weeks. Intervention time was 8 minutes to 70 minutes and most interventions were done in occupational therapy room or sensory integration therapy room. According to the result of quality level evaluation, 4 papers out of 17 papers were on high level and remaining papers were on intermediate level. However, there was no study which included intervention blind. Conclusion : Suggested standards that need to be supplemented and discussions on qualitative improvement including repetitive research on the mediation effect during the application of the single subject research methodology, the securement of adequate data sections, and processing of a mediation blind. It is expected to be used as basic data for conducting a better qualitative research in the future.

• Journal of Intelligence and Information Systems
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• v.14 no.3
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• pp.59-76
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• 2008

In this paper, we propose an agent architecture called L-CAA that is quite effective in real-time dynamic environments. L-CAA is an extension of CAA, the behavior-based agent architecture which was also developed by our research group. In order to improve adaptability to the changing environment, it is extended by adding reinforcement learning capability. To obtain stable performance, however, behavior selection and execution in the L-CAA architecture do not entirely rely on learning. In L-CAA, learning is utilized merely as a complimentary means for behavior selection and execution. Behavior selection mechanism in this architecture consists of two phases. In the first phase, the behaviors are extracted from the behavior library by checking the user-defined applicable conditions and utility of each behavior. If multiple behaviors are extracted in the first phase, the single behavior is selected to execute in the help of reinforcement learning in the second phase. That is, the behavior with the highest expected reward is selected by comparing Q values of individual behaviors updated through reinforcement learning. L-CAA can monitor the maintainable conditions of the executing behavior and stop immediately the behavior when some of the conditions fail due to dynamic change of the environment. Additionally, L-CAA can suspend and then resume the current behavior whenever it encounters a higher utility behavior. In order to analyze effectiveness of the L-CAA architecture, we implement an L-CAA-enabled agent autonomously playing in an Unreal Tournament game that is a well-known dynamic virtual environment, and then conduct several experiments using it.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.279-282
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• 2017

Kinect depth sensor, a depth camera developed by Microsoft as a natural user interface for game appeared as a very useful tool in computer vision field. In this paper, due to kinect's depth sensor and its high frame rate, we developed a distance measurement system using Kinect camera to test it for unmanned vehicles which need vision systems to perceive the surrounding environment like human do in order to detect objects in their path. Therefore, kinect depth sensor is used to detect objects in its field of view and enhance the distance measurement system from objects to the vision sensor. Detected object is identified in accuracy way to determine if it is a real object or a pixel nose to reduce the processing time by ignoring pixels which are not a part of a real object. Using depth segmentation techniques along with Open CV library for image processing, we can identify present objects within Kinect camera's field of view and measure the distance from them to the sensor. Tests show promising results that this system can be used as well for autonomous vehicles equipped with low-cost range sensor, Kinect camera, for further processing depending on the application type when they reach a certain distance far from detected objects.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.100-108
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• 2018

This paper describes a design of scalable RSA public-key cryptography processor supporting four key lengths of 512/1,024/2,048/3,072 bits. The modular multiplier that is a core arithmetic block for RSA crypto-system was designed with 32-bit datapath, which is based on the CIOS (Coarsely Integrated Operand Scanning) Montgomery modular multiplication algorithm. The modular exponentiation was implemented by using L-R binary exponentiation algorithm. The scalable RSA crypto-processor was verified by FPGA implementation using Virtex-5 device, and it takes 456,051/3,496347/26,011,947/88,112,770 clock cycles for RSA computation for the key lengths of 512/1,024/2,048/3,072 bits. The RSA crypto-processor synthesized with a $0.18{\mu}m$ CMOS cell library occupies 10,672 gate equivalent (GE) and a memory bank of $6{\times}3,072$ bits. The estimated maximum clock frequency is 147 MHz, and the RSA decryption takes 3.1/23.8/177/599.4 msec for key lengths of 512/1,024/2,048/3,072 bits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.7C
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• pp.647-657
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• 2005

In this paper, we proposed a new lifting architecture for JPEG2000 and implemented to ASIC. We proposed a new cell to execute unit calculation of lifting using the property of lifting which is the repetitious arithmetic with same structure, and then recomposed the whole lifting by expanding it. After the operational sequence of lifting arithmetic was analyzed in detail and the causality was imposed for implementation to hardware, the unit cell was optimized. A new lifting kernel was organized by expanding simply the unit cell, and a lifting processor was implemented for Motion JPEG2000 using it. The implemented lifting kernel can accommodate the tile size of 1024$\times$1024, and support both lossy compression using the (9,7) filter and lossless compression using (5,3) filter. Also, it has the same output rate as input rate, and can continuously output the wavelet coefficients of 4 types(LL, LH, HL, HH) at the same time. The implemented lifting processor completed a course of ASIC using 0.35$\mu$m CMOS library of SAMSUNG. It occupied about 90,000 gates, and stably operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the improved operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the performance can be identified in comparison with the previous researches and commercial IPs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10A
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• pp.1223-1229
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• 2004

A variable-gain low-voltage low noise amplifier MMIC operating at 5GHz frequency band is designed and implemented using the ETRI 0.5$\mu\textrm{m}$ GaAs MESFET library process. This low noise amplifier is designed to have the variable gain for adaptive antenna array combined in HIPERLAN/2. The feedback circuit of a resistor and channel resistance controlled by the gate voltage of enhancement MESFET is proposed for the variable-gain low noise amplifier consisted of cascaded two stages. The fabricated variable gain amplifier exhibits 5.5GHz center frequency, 14.7dB small signal gain, 10.6dB input return loss, 10.7dB output return loss, 14.4dB variable gain, and 2.98dB noise figure at V$\_$DD/=1.5V, V$\_$GGl/=0.4V, and V$\_$GG2/=0.5V. This low noise amplifier also shows-19.7dBm input PldB, -10dBm IIP3, 52.6dB SFDR, and 9.5mW power consumption.