• Title/Summary/Keyword: Level switch

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Modeling of Static Var Compensator with Hybrid Cascade 5-level PWM Inverter Using Circuit DQ Transformation (회로 DQ 변환을 이용한 하이브리드 Cascade 5-레벨 PWM 인버터를 포함하는 무효전력보상기의 모델링)

  • 최남섭
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.6 no.3
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    • pp.421-426
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    • 2002
  • Hybrid cascade multilevel PWM inverter has advantages of hybrid structure which enhances the better utilization of power semiconductor switches, that is, both hi호 power-low frequency switch, GTO and low power-high frequency switch, IGBT can be used in the same circuit. In this paper, a static var compensator using hybrid cascade 5-level PWM inverter is presented for high voltage/high power applications. The proposed system is modelled by circuit DQ transformation, and thus an equivalent circuit is obtained which reveals the important characteristics of the system and lead to the related equations. Finally, circuit structure and characteristics is presented and the validity of the characteristics analysis is shown through PSIM simulation.

A Novel Ripple-Reduced DC-DC Converter

  • Tao, Yu;Park, Sung-Jun
    • Journal of Power Electronics
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    • v.9 no.3
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    • pp.396-402
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    • 2009
  • A DC/DC converter generally needs to work under high switching frequency when used as an adjustable power supply to reduce the size of magnetic elements such as inductors, transformers and capacitors, but with the rising of the switch frequency, the switch losses will increase and the efficiency will reduce. Recently, to solve these problems, research is actively being done on a soft switching method that can be applied under high frequency and on a PWM converter that can be applied under low frequency such as a multi-level topology. In this paper a novel DC-DC conversion method for reducing the ripple of output voltage is proposed. In the proposed converter, buck converters are connected in series to generate the output voltage. By using this method, the ripple of output voltage can be reduced compared to a conventional buck converter. Particularly when output voltage is low, the number of acting switching elements is less and the result of ripple reduction is more obvious. It is expected that the converter proposed in this paper could be very useful in the case of wide-range output voltage.

Switch Level Logic Simulator Using Polynomial MOS Delay Model (다형식 MOS 지연시간 모델을 이용한 스윗치레벨 논리 시뮬레이터)

  • Jun, Young-Hyun;Jun, Ki;Park, Song-Bai
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.6
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    • pp.700-709
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    • 1988
  • A new technique is proposed for switch-level logic simulation for NMOS and CMOS logic circuits. For the simple inverter the rise or fall delay time is approximated by a product of polynomials of the input waveform slope, the output loading capacitance and the device configuration ratio, the polynomial coefficients being so determined as to best fit the SPICE simuladtion results for a given fabrication process. This approach can easily and accurately be extened to the case of multiple input transitions. The simulation results show that proposed method can predict the delay times within 5% error and with a speed up by a factor of three orders of magnitude for several circuits tested, as compared with the SPICE simulation.

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An Implementation of the switch-Level Fault Simulator for CMOS Circuits with a Gate-to-Drain/Source short Fault (게이트와 드레인/소오스 단락결함을 갖는 CMOS 회로의 스위치 레벨 결함 시뮬레이터 구현)

  • 정금섭;전흥우
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.4
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    • pp.116-126
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    • 1994
  • In this paper, the switch-level fault simulator for CMOS circuits with a gate-to-drain/source short fault is implemented. A fault model used in this paper is based on the graphical analysis of the electrical characteristics of the faulty MOS devices and the conversion of the faulty CMOS circuit to the equivalent faulty CMOS inverter in order to find its effect on the successive stage. This technique is very simple and has the increased accuracy of the simulation. The simulation result of the faulty circuit using the implemented fault simulator is compared with the result of the SPICE simulation.

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A Japanese National Project for Superconductor Network Devices

  • Hidaka, M.
    • Progress in Superconductivity
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    • v.5 no.1
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    • pp.1-4
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    • 2003
  • A five-year project for Nb-based single flux quantum (SFQ) circuits supported by Japan's Ministry of Economy Trade and Industry (METI) in Japan was started in September 2002. Since April 2003, the New Energy and Industrial Technology Development Organization (NEDO) has supported this Superconductor Network Device Project. The aim of the project is to improve the integration level of Nb-based SFQ circuits to several ten thousand Josephson junctions, in comparison with their starting integration level of only a few thousand junctions. Actual targets are a 20 GHz dual processor module for the servers and a 0.96 Tbps switch module for the routers. Starting in April 2003, the Nb project was merged with SFQ circuit research using a high-T$_{c}$ superconductor (HTS). The HTS research targets are a wide-band AD converter for mobile-phone base stations and a sampling oscilloscope for wide-band waveform measurements.

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High Efficiency H-Bridge Multilevel Inverter System Using Bidirectional Switches (양방향 스위치를 이용한 고효율 H-Bridge 멀티레벨 인버터 시스템)

  • Lee, Hwa-Chun;Hwang, Jung-Goo;Kim, Sun-Pil;Choi, Woo-Seok;Lee, Sang-Hyeok;Park, Seong-Mi;Park, Sung-Jun
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.28 no.10
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    • pp.16-26
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    • 2014
  • This paper proposes new 13-level inverter topology and DC/DC converter buck-boost structure topology for multilevel, compounding uni-directional and bi-directional switches, and proposes high-efficient multilevel inverter system in which the proposed two PCS(Power Conditioning System) was connected in series. In proposed multilevel inverter of forming a output 13-level phase voltage by using total 18 switching parts, Then bi-directional switch has a characteristic of reducing conduction loss and controlling the reactive power effectively by separating electrically from the neutral point. DC/DC converter for supplying in dependent 3 DC voltage to the proposed multi-level inverter generates 180-degree phase shifted PWM by the symmetrically combined structure of 2 buck-boost converter and twice switching frequency efficiency can be obtained, meanwhile, the converter can step up/down the output voltage and 20% output can be generated comparing the input voltage. This proposed system is verified with the simulation and laboratory test.

Issues of Workplace in Korea: How to Inspire Temporary Workers?

  • Yang, Hoe-Chang;Khan, Tasnuva
    • Asian Journal of Business Environment
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    • v.3 no.1
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    • pp.23-27
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    • 2013
  • Purpose - This study will focus on motivation of temporary workers working in distributors as well as generic companies, especially MPS (motivating potential score) proposed by job characteristics model. We think that temporary workers required intrinsic motivation in order to commit with their organization because they are difficult switch-regular workers due to glass ceiling. Research design, data, methodology - This study operates a survey targeting temporary workers, specifically, we used 144 copies except uncollected copies and dishonesty response of total 165 copies on analysis. We used multiple regression and 3 step regression to investigate the proposed model. Results - The high level of perceived distributional justice and procedural justice was increased the level of organizational commitment, respectively. And, MPS was increased the level of organizational commitment, too. Finally, this study showed that both justice and Job characteristics were very important to increase organizational commitment. Conclusions - In order to inspire temporary workers, the company provides placing enough considering job characteristics as well as fairness of the procedure and distribution. Also, to more fully understand the underlying processes between HRM (Human Resource Management) concepts, new fundamental methods may be required such as switch full-time opportunities.

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A Channel Allocation and Data Delivery Scheme Considering Channel Overlapping in Wireless Tactical Networks (군 전술망의 무선 이동 통신 체계의 통신 범위 중첩을 고려한 채널 할당 기법과 데이터 전달 기법)

  • Shin, Hyun-Sup;Chae, Sung-Yoon;Kang, Kyung-Ran;Cho, Young-Jong
    • Journal of the Korea Institute of Military Science and Technology
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    • v.14 no.3
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    • pp.501-508
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    • 2011
  • In this paper, we propose a channel allocation algorithm of MSAP(Mobile Subscriber Access Point) and data delivery scheme exploiting the symbol level network coding. The network is comprised of TS(Tactical Switch) as a backbone node, MSAPs, and TMFTs(Tactical Multi-Function Terminal). The TS performs the channel allocation considering the communication range overlapping between the neighboring MSAPs and applies the symbol level network coding, if necessary, depending on the position of the TMFTs. Assuming the number of available antennas of TMFT and MSAP will be extended to two from one, we propose two schemes: single mode and dual mode. Through the simulation, we show that the proposed delivery scheme provides higher delivery ratio and lower delivery delay compared with the legacy store-and-forward scheme.

Floating Power Supply Based on Bootstrap Operation for Three-Level Neutral-Point-Clamped Voltage-Source Inverter

  • Nguyen, Qui Tu Vo;Lee, Dong-Choon
    • Proceedings of the KIPE Conference
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    • 2011.11a
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    • pp.3-4
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    • 2011
  • This paper presents a survey of floating power supply based on bootstrap operation for three-level voltage-source inverters. The floating power supply for upper switches is achieved by the bootstrap capacitor charged during on-time of the switch underneath. Hence, a large number of bulky isolated DC/DC power supplies for each gate driver are reduced. The Pspice simulation results show the behavior of bootstrap devices and the performance of bootstrap capacitor voltage.

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The Developments of State CHDL and Two-Level Minimizer for State Machine Synthesizer (상태합성기(State Machine Synthesizer) 설계를 위한 상태 CHDL 개발 및 Two-level minimizer 개발에 관한 연구)

  • 김희석;이근만;임인칠
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.29A no.4
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    • pp.83-90
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    • 1992
  • The state machine synthesizer is widely used to FSM synthesis. In this paper, we developed the state machine description language "state CHDL" such as IF, THEN, ELSE, SWITCH, CASE statements. Also, an algorithm for efficient state minimization and two level minimizer of FSM and graphical user interface-pin map window, supporting the designer with input-ouput effency, are presented.

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