• 한국전기전자재료학회논문지
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• 제11권10호
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• pp.918-923
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• 1998

Poly-silicon thin film transistors were fabricated on quartz substrates by high temperature processes. Electrical characteristics were measured and compared for 3 transistor structures of Standard Inverted Gate(SIG), Lightly Doped Drain(LDD), and Dual Gate(DG). Leakage currents of DG and LDD TFT's were smaller that od SIG transistor, while ON-current of LDD transistor is much smaller than that of SIG and DG transistors. Temperature dependence of the leakage currents showed that SIG and DG TFT's had thermal generation current at small drian bias and Frenkel-Poole emission current at hight gate and drain biases, respectively. In case of LDD transistor, thermal generation was the dominant mechanism of leakage current at all bias conditions. It was found that the leakage current was closely related to the reduction of the electric field in the drain depletion region.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.50-53
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• 2001

In this study, gate leakage current mechanism has been analyzed for GaAs MESFET with different temperatures ranging from 27$^{\circ}C$ to 300$^{\circ}C$ . It is expected that the thermionic and field emission at the MS contact will dominate the current flow. Thermal cycle is applied to test the reliability of the device. From the results, it is proved that thermal stress gradually increases the gate leakage current at the same bias conditions and leads to the breakdown and failure mechanism which is critical in the field equipment. Finally the gate contact under the repeated thermal shock has been tested to check the quality of Schottky barrier and the current will be expressed in the analytical from to associate with the electrical characteristics of the device.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1250-1252
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• 1993

Enhancement mode n-channel TFT leakage current(off current : $V_G<0$) that is little agreement on the conduction mechanism is major disadvantage of poly-silicon TFT in practical use, characteristic analysis and model ing. In this paper, new modeling of leakage current is proposed. The activation energy of leakage current, which is dependent on gate voltage, and leakage current dependent on poly silicon thickness are plausibly explained with this model. This model indicate that the reduction of leakage current is attributable to a decrease of maximum laterial electric field strength in the drain depletion region and to the density of trap.

• 한국전기전자재료학회논문지
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• 제14권2호
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• pp.111-116
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• 2001

Poly-Si TFT's(Polysilicon thin filmtransistors) have been actively studied due to their applications in active matrix liquid crystal displays and active pull-up devices of CMOS SRAM's. For such applications, the leakage current has to be in the range of sub-picoampere. However, poly-Si TFT's suffer from anomalous high leakage currents, which is attributed to the emission of the traps present at gain boundaries in the drain junction. The leakage current has been analyzed by the field emission via grain-boundary traps and thermionic field emission over potential barrier located at the grain boundary. We found that the models proposed before are not consistent with the experimental results at far as drain-offset poly-Si TFT's we fabricated concern. In this paper, leakage current of drain-offset poly-Si TFT's with different offset lengths was studied. A conduction model based on the thermionic emission of the tunneling electrons is developed to identify the leakage mechanism. It was found that the effective grain size of the drain-offset region is important factor in the leakage current. A good agreement between experimental and simulated results of the leakage current is obtained.

• KEPCO Journal on Electric Power and Energy
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• 제2권2호
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• pp.223-225
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• 2016

The newly proposed analysis method using a direct-current current-voltage (DCIV) simulation is introduced for investigating leakage current composing MOS transistor. From comparing the density and location of traps using DCIV method and investigating the leakage current of gate channel transistor, we proposed the graphical analysis method to correlate the DCIV current and leakage mechanism by the traps. And, our graphical method intuitively explains that leakage current in MOS transistor is well correlated with the DCIV current of the MOS transistor arrays due to two kinds of traps created by Fowler-Nordheim (F-N) stress and Hot carrier stress, respectively.

• 한국재료학회지
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• 제11권2호
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• pp.151-154
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• 2001

상부전극, Pt, Ir, 그리고 $IrO_2$, 에 따라 수소 열처리전과 후, 그리고 회복열처리시 누설전류특성을 고찰하였다. Pt/PLZT/Pt 케페시터는 수소열처리 후에 다시 회복열처리를 수행하면 완전히 이력곡선의 회복을 보이며 또한 피로특성도 거의 회복 된다. Pt과 IrO$_2$ 상부전극의 경우의 진 누설전류 특성은 열처리조건에 관계없이 강한 시간 의존성을 갖는 space-charge influenced injection모델에 적합하다. 반면에 Ir 상부전극의 경우는 Ir과 PLZT 사이의 계면에 헝성된 전도성 상인 $IrO_2$로 인해 높은 누설전류 밀도를 보이면서 relaxation current 영역이 없이 steady state 영역을 보이는, 주로 Schottky barrier 모델에 의해 설명된다.

• 전기의세계
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• 제29권5호
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• pp.303-311
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• 1980

The hazards of electrical shock are well known, but the conventional ground fault circuit breakers did not provide the statis factory safety for human body. Thus this paper considers the standards of performance that they must meet, and describes the new tripping mechanism the operations and the improvements. The experiment at new G.F.C.I. indicates maximum tripping time 25msec minimum sensitive leakage current 25mA and maximum nonaperation leakage current 15mA.

• 마이크로전자및패키징학회지
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• 제11권3호
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• pp.91-97
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• 2004

PZT 박막을 rf-마그네트론 스퍼터링으로 $Pt/Ti/SiO_2/Si$ 기판 위에 형성시켰다. $5\%$ 과잉 PbO 를 포함한 bulk PZT 타겟을 사용하였다. 상온에서 PZT 박막을 얇게 입힌 후 나머지 두께를 $650^{\circ}C$에서 in-situ 방법으로 형성시켰다. 강유전 특성을 갖는 PZT 상은 $650^{\circ}C$에서 형성되었다. 2단계 스퍼터링에 의해 누설전류 특성을 크게 증진시킬 수 있었고, 적절한 두께의 상온층을 포함시킨 경우 $2{\times}10^{-7}A/cm^2$의 매우 작은 누설전류를 나타냈다. 누설전류 기구에 대한 조사 결과, 여러 조건에서 제조된 PZT 박막의 전기전도는 모두 bulk-limit 기구에 의한 것임을 알 수 있었다.

• 전자공학회논문지A
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• 제32A권2호
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• pp.324-331
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• 1995

The leakage current characteristics of the low temperature processed LDD structure poly-Si TFT is analyzed. The excimer laser technology was applied to the recrystallization process of poly-Si film and the maximum processing temperature was retained under 600.deg.C. From the fabricated LDD space 0.3.mu.m to 3$\mu$m, the best on/off current ration could be obtained with the 1.3$\mu$m LDD space. And the threshold voltage did not increase more than 4V over 0.8$\mu$m LDD space. The characteristics of leakage current was compared to non-LDD structure TFT to analyze the mechanism of leakage current. Consequently, it could be concluded that the leakage current is strongly affected by the trap states as well as high electric field between gate and drain.

• Journal of Power Electronics
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• 제16권3호
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• pp.970-981
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• 2016

Leakage currents occur in pulse-width-modulated voltage source inverter (PWM-VSI)-fed permanent magnet synchronous motor (PMSM) drives for air-conditioners, which seriously affect system safety and operation performance. High accuracy modeling and prediction of leakage currents are key issues for the design and implementation of air-conditioning products. In this study, the generation mechanism of leakage currents is discussed. A systematic modeling approach of leakage currents is proposed, including the modeling of leakage current sources and leakage current paths. By using the proposed approach, the complete model of leakage currents in PWM-VSI-fed PMSM drives for air-conditioners has been developed based on the extraction of all parameters. A comparison between the simulated leakage currents based on the developed model and measured leakage currents in the outdoor unit of an air-conditioning product is conducted. The comparison verifies the effectiveness of the proposed modeling approach, and the developed model exhibits high accuracy within a wide frequency range.