• Macromolecular Research
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• v.15 no.2
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• pp.114-128
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• 2007

Polyimides are one of the most important classes of polymers used in the microelectronics and photoelectronics industries. Because of their high thermal stability, chemical resistance, and good mechanical and electric properties, polyimides are often applied in photoresists, passivation and dielectric films, soft print circuit boards, and alignment films within displays. Recently, fully aliphatic and alicyclic polyimides have found applications as optoelectronics and inter layer dielectric materials, due to their good transparencies and low dielectric constants $(\varepsilon)$. The low molecular density, polarity and rare probability of forming inter- or intra-molecular charge transfers, resulting in lowering of the dielectric constant and high transparency, are the most striking characteristics of aliphatic polyimide. However, the ultimate end use of polyimides derived from aliphatic monomers is in their targeted applications that need less stringent thermal requirements. Much research effort has been exerted in the development of aliphatic polyimide with increased thermal and mechanical stabilities, while maintaining their transparencies and low dielectric constants, by the incorporation of rigid moieties. In this article, the recent research process in synthesizing fully aliphatic polyimides, with improved dimensional stability, high transparency and low $\delta$values, as well as the characterizations and future scope for their application in micro electric and photo-electronic industries, is reviewed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.7
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• pp.569-574
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• 2007

In this paper, the reliability (NBTI degradation: ${\Delta}V_{th}$) and device characteristic of nano-scale PMOSFET with plasma nitrided oxide (PNO) is characterized in depth by comparing those with thermally nitrided oxide (TNO). PNO case shows the reduction of gate leakage current and interface state density compared to TNO with no change of the $I_{D.sat}\;vs.\;I_{OFF}$ characteristics. Gate oxide capacitance (Cox) of PNO is larger than TNO and it increases as the N concentration increases in PNO. PNO also shows the improvement of NBTI characteristics because the nitrogen peak layer is located near the $Poly/SiO_2$ interface. However, if the nitrogen concentration in PNO oxide increases, threshold voltage degradation $({\Delta}V_{th})$ becomes more degraded by NBT stress due to the enhanced generation of the fixed oxide charges.

• Journal of the Korean Chemical Society
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• v.43 no.3
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• pp.315-320
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• 1999

Novel electroluminescent materials, polymer material, PU-BCN and low molar mass material, D-BCN with the same chromophores were designed and synthesized. A molecular structure of chromophore was composed of bisstyrylbenzene derivative with cyano groups as electron injection and transport and phenylamine groups as hole injection and transport. Device structures with PU-BCN and D-BCN as an emission layer were fa-bricated, which were a single-layer device(SL), Indium-tin oxide(ITO)/emission layer/MgAg, and two kinds of double-layer devices which were composed of ITO/emission layer/oxadiazole derivative/MgAg as a DL-E device and ITO/triphenylamine derivative/emission layer/MgAg as a DL-H device. The two emission materials, PU-BCN and D-BCN with the same emission-chromophore were evaluated as having excellent performance of charge injection and transport and revealed almost the same emission characteristics in high current density. EL emission maximum peaks of two material were detected at about 640 nm wavelength of red emission region.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.307.2-307.2
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• 2016

In this study, we synthesized Au nanoparticles (AuNPs) in polyacrylonitrile (PAN) thin films using a simple annealing process in the solid phase. The synthetic conditions were systematically controlled and optimized by varying the concentration of the Au salt solution and the annealing temperature. X-ray photoelectron spectroscopy (XPS) confirmed their chemical state, and transmission electron microscopy (TEM) verified the successful synthesis, size, and density of AuNPs. Au nanoparticles were generated from the thermal decomposition of the Au salt and stabilized during the cyclization of the PAN matrix. For actual device applications, previous synthetic techniques have required the synthesis of AuNPs in a liquid phase and an additional process to form the thin film layer, such as spin-coating, dip-coating, Langmuir-Blodgett, or high vacuum deposition. In contrast, our one-step synthesis could produce gold nanoparticles from the Au salt contained in a solid matrix with an easy heat treatment. The PAN:AuNPs composite was used as the charge trap layer of an organic nano-floating gate memory (ONFGM). The memory devices exhibited a high on/off ratio (over $10^6$), large hysteresis windows (76.7 V), and a stable endurance performance (>3000 cycles), indicating that our stabilized PAN:AuNPs composite film is a potential charge trap medium for next generation organic nano-floating gate memory transistors.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.159-167
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• 2005

Quantization effects (QEs), which manifests when the device dimensions are comparable to the de Brogile wavelength, are becoming common physical phenomena in the present micro-/nanometer technology era. While most novel devices take advantage of QEs to achieve fast switching speed, miniature size and extremely small power consumption, the mainstream CMOS devices (with the exception of EEPROMs) are generally suffering in performance from these effects. In this paper, an analytical model accounting for the QEs and poly-depletion effects (PDEs) at the silicon (Si)/dielectric interface describing the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of MOS devices with thin oxides is developed. It is also applicable to multi-layer gate-stack structures, since a general procedure is used for calculating the quantum inversion charge density. Using this inversion charge density, device characteristics are obtained. Also solutions for C-V can be quickly obtained without computational burden of solving over a physical grid. We conclude with comparison of the results obtained with our model and those obtained by self-consistent solution of the $Schr{\ddot{o}}dinger$ and Poisson equations and simulations reported previously in the literature. A good agreement was observed between them.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.12
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• pp.1122-1127
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• 1998

Group II-AF_2$films such as $CaF_2$, $SrF_2$, and $BaF_2$ have been commonly used many practical applications such as silicon on insulatro(SOI), three-dimensional integrated circuits, buffer layers, and gate dielectrics in filed effect transistor. This paper presents electrical and structural properties of fluoride films as a gate dielectric layer. Conventional gate dielectric materials of TFTs like oxide group exhibited problems on high interface trap charge density($D_it$), and interface state incorporation with O-H bond created by mobile hydrogen and oxygen atoms. To overcome such problems in conventional gate insulators, we have investigated $CaF_2$ films on Si substrates. Fluoride films were deposited using a high vacuum evaporation method on the Si and glass substrate. $CaF_2$ films were preferentially grown in (200) plane direction at room temperature. We were able to achieve a minimum lattice mismatch of 0.74% between Si and $CaF_2$ films. Average roughness of $CaF_2$ films was decreased from 54.1 ${\AA}$ to 8.40 ${\AA}$ as temperature increased form RT and $300^{\circ}C$. Well fabricated MIM device showed breakdown electric field of 1.27 MV/cm and low leakage current of $10^{-10}$ A/$cm^2$. Interface trap charge density between $CaF_2$ film and Si substrate was as low as $1.8{\times}10^{11}cm^{-2}eV^{-1}$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.469-472
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• 1999

CeO$_2$ thin films have used in wide applications such as SOI, buffer layer, antirflection coating, and gate dielectric layer. CeO$_2$takes one of the cubic system of fluorite structure and shows similar lattice constant (a=0.541nm) to silicon (a=0.543nm). We investigated CeO$_2$films as buffer layer material for nonvolatile memory device application of a single transistor. Aiming at the single transistor FRAM device with a gate region configuration of PZT/CeO$_2$ /P-Si , this paper focused on CeO$_2$-Si interface properties. CeO$_2$ films were grown on P-type Si(100) substrates by 13.56MHz RF magnetron sputtering system using a 2 inch Ce metal target. To characterize the CeO$_2$ films, we employed an XRD, AFM, C-V, and I-V for structural, surface morphological, and electrical property investigations, respectively. This paper demonstrates the best lattice mismatch as low as 0.2 % and average surface roughness down to 6.8 $\AA$. MIS structure of CeO$_2$ shows that breakdown electric field of 1.2 MV/cm, dielectric constant around 13.6 at growth temperature of 200 $^{\circ}C$, and interface state densities as low as 1.84$\times$10$^{11}$ cm $^{-1}$ eV$^{-1}$ . We probes the material properties of CeO$_2$ films for a buffer layer of FRAM applications.

• Journal of the Korean Society for Heat Treatment
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• v.30 no.2
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• pp.61-66
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• 2017

$SnO_2$ was electrodeposited on nodule-type Cu foil at varing current density and electrodeposition time. Unlike the previous research results, when the anodic current is applied, the $SnO_2$ layer was not electrodeposited and the substrate is corroded. When the cathodic current was applied, the $SnO_2$ layer could be successfully deposited. At this time, the surface microstructure of the powdery type was observed, which showed similar crystallinity to amorphous and had a very large surface area. Crystallinity increased after low-temperature heat treatment at $250^{\circ}C$ or lower. As a result of evaluating the charge/discharge performances as an anode material for lithium ion battery, it was confirmed that the capacity of the heat treated $SnO_2$ was increased more than 2 times, but it still showed a limit point showing initial low coulombic efficiency and low cyclability. However, it was confirmed that the battery performances may be enhanced through optimizing the electrodeposition process and introducing post heat treatment.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1379-1381
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• 1998

Powder electroluminescent device (PELD) structured conventionally dielectric and phosphor layer, between electrode and their layer fabricated by screen printing splaying or spin coating method. To promote performance of PELDs, we approached the experiments for different structure and thickness variation of PELD. Thickness variation($30{\mu}m{\sim}130{\mu}m$) was taken. To investigate electrical and optical properties of PELDs, EL spectrum, transferred charge density using Sawyer-Tower's circuit brightness was measured. Variation of structure in PELDs was as follows: WK-1 (ITO/BaTiO3/ZnS:Cu/Silver paste), WK-2 (ITO/BaTiO3/ZnS:Cu/BaTiO3/ZnS:Silver paste), WK-3 (ITO/BaTiO3/ZnS:Cu/BaTiO3/Silver paste), WK-4(ITO/BaTiO3+ZnS:Cu/Silver paste) As a result, structure of the highest brightness appeared WK-4 possessed 60 ${\mu}m$ thickness. The brightness was 2719 cd/$m^2$ at 100V, 400Hz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.973-976
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• 2004

The results of numerous studies in III-V semiconductors show that sulfur treatment improves the electrical parameters of III-V compound devices. In this article, we examine the effects of sulfidation of HgCdTe surface on the interfacial characteristics of metal-ZnS-HgCdTe structures. Different from sulfidation in III-V material, S can not be act as an impurity because II-S compounds (ZnS, CdS) generally used as passivant for HgCdTe. Our studies of sulfur-treatment on HgCdTe surface show that sulfur agent forms the S- S, II-S bonds at the surface layer. These bonds are very effective to improve the electrical properties of ZnS layer on HgCdTe by reducing the possibility of native oxides formation. After the sulfidation process, MIS capacitors of HgCdTe show great improvement in electrical properties, such as low density of fixed charge and reduced hystereisis width.