• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.9
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• pp.1611-1614
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• 2010

The explosion of a nuclear weapon radiates a gamma-ray in the form of a transient pulse. If the gamma-ray introduces to semiconductor devices, much Electron-Hole Pairs(EHPs) are generated in depletion region of the devices[7]. as a consequence of that, high photocurrent is created and causes upset, latchup and burnout of semiconductor devices[8]. This phenomenon is known for Transient Radiation Effects on Electronics(TREE), also called dose-rate effects. In this paper 3D structure of inverter and NAND gate device was designed and transient pulse gamma-ray was modeled. So simulation for transient radiation effect on inverter and NAND gate was accomplished and mechanism for upset and latchup was analyzed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.140-141
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• 2006

Background doping concentration (BDC) is proven to be a critical factor to affect the high current behavior of the extended drain NMOSFET (EDNMOS) devices. The EDNMOS device with low BDC suffers from strong snapback in the high current region, which results in poor electrostatic discharge (ESD) protection performance and high latchup risk. However, the strong snapback can be avoided in the EDNMOS device with high BDC. This implies that both the good ESD protection performance and the latchup immunity can be realized in terms of the EDNMOS by properly controlling its BDC.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.1023-1026
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• 2013

The electronic equipment which was exposed to high level pulsed radiation is damaged as Upset, Latchup, and Burnout. Those damages has come from the instantaneous photocurrent from electron-hole pairs generated in itself. Such damages appeared as losses of power in military weapon system or of blackout in aerospace equipment and eventually caused in gross loss of national. In this paper, we have implemented a RDC(Radiation detection and control module) as part of the radiation protection technology of the electronic equipment or devices from the pulsed gamma radiation. The RDC which is composed of pulsed gamma-ray detection sensor, signal processors, and pulse generator is designed to protect the important electronic circuits from the pulse radiation. To verify the functionality of the RDC, LM118s which had damaged by the pulse radiation were tested. The test results showed that the test sample applied with a RDC was worked well in spite of the irradiation of the same pulse radiation. Through the experiments we could confirm that the radiation protection technology implemented with RDC had the functionality of radiation protection to the electronic devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.178-179
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• 2005

ESD(Electrostatic Discharge) 보호에 응용되는 소자는 ESD가 발생했을 때, 빠르게 턴-온되어 외부로부터 EOS(Electric OverStress)를 차단함으로서 집적회로 내부의 코어를 보호해 주어야 한다. 이러한 기능에 충실한 LVTSCR(Low-Voltage Silicon Controlled Rectifier)은 트리거링 전압을 기존의 SCR보다 낮추어 ESD에 대해 민감한 반응을 할 수 있도록 개선한 소자이다. 그러나 트리거링 전압을 낮추면서 래치업 전압 또한 낮아지는 특성이 trade-off 관계로 맞물려 있어, LVTSCR의 단점인 낮은 래치업 전압을 효과적으로 다루는 것이 큰 이슈가 되고 있다. 본 논문에서는 LVTSCR의 ESD 보호에 대한 응용시 발생 가능한 래치업을 차폐하는 회로적 방법을 제시하였다. 제시된 새로운 구조의 차폐회로는 LVTSCR에서 래치업이 발생했을 때, 천이 전류를 감지하여 래치업이 발생되는 소자에 대한 전원을 스스로 차폐시켜 래치업에 대한 안정성을 시뮬레이션으로 검증하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.1-6
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• 2009

The holding voltage of high-voltage devices under the snapback breakdown condition has been known to be much smaller than the operating voltage. Such characteristics cause high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used as the ESD(ElectroStatic Discharge) power clamp circuit. A new latchup-free design of the ESD power clamp circuit with stacked-bipolar devices is proposed and successfully verified in a $0.35{\mu}m$ 3.3V/60V BCD(Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the operating voltage. Proposed power clamp operates safely because of the high holding voltage. From the measurement on the devices fabricated using a $0.35{\mu}m$ BCD Process, it was observed that the proposed ESD power clamp can provide 800% higher ESD robustness per silicon area as compared to the conventional clamps with a high-voltage diode.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.1-6
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• 2008

The holding voltage of the high-voltage MOSFETs in snapback condition is much smaller than the power supply voltage. Such characteristics may cause the latcup-like problems in the Smart Power ICs if these devices are directly used in the ESD (Electrostatic Discharge) power clamp. In this work, a latchup-free design based on the Drain-Extended PMOS (DEPMOS) adopting gate VDD structure is proposed. The operation region of the proposed gate-VDD DEPMOS ESD power clamp is below the onset of the snapback to avoid the danger of latch-up. From the measurement on the devices fabricated using a $0.35\;{\mu}m$ BCD (Bipolar-CMOS-DMOS) Process (60V), it was observed that the proposed ESD power clamp can provide 500% higher ESD robustness per silicon area as compared to the conventional clamps with gate-driven LDMOS (lateral double-diffused MOS).

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.05a
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• pp.63-66
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• 2005

A soft error rate neutrons is a growing problem for integrated circuits with technology scaling. In the acceleration test with high-density neutron beam, a latch-up prohibits accurate estimations of the soft error rate (SER). This paper presents results of analysis for the latch-up characteristics in the circumstance corresponding to the acceleration SER test for SRAM. Simulation results, using a two-dimensional device simulator, show that the deep p-well structure has better latch-up Immunity compared to normal twin and triple well structures. In addition, it is more effective to minimize the distance to ground power compared with controlling a path to the $V_{DD}$ power.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.10
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• pp.1421-1424
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• 2013

The electronic equipment which is exposed to high level pulsed radiation is damaged by Upset, Latchup, and Burnout. Those damages come from the instantaneous photocurrent from electron-hole pairs generated in itself. Such damages appear as losses of a power in military weapon system or as a blackout in aerospace equipment and eventually caused in gross loss of national power. In this paper, we have implemented a RDC(Radiation detection and control module) as a part of the radiation protection technology of the electronic equipment or devices from the pulsed gamma radiation. The RDC, which is composed of pulsed gamma-ray detection sensor, signal processors, and pulse generator, is designed to protect the an important electronic circuits from the a pulse radiation. To verify the functionality of the RDC, LM118s, which had damaged by the pulse radiation, were tested. The test results showed that the test sample applied with the RDC was worked well in spite of the irradiation of a pulse radiation. Through the experiments we could confirm that the radiation protection technology implemented with the RDC had the functionality of radiation protection for the electronic devices.

• Proceedings of the KAIS Fall Conference
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• 2011.12b
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• pp.660-663
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• 2011

우주방사선이나 과도펄스(Transient Radiation) 형태의 감마 방사선이 반도체에 조사되면 소자 내부에서 짧은 시간에 다량의 전하가 생성된다. 이 전하들과 증폭된 과전류는 소자의 고장(Upset, Latchup)과 오동작을 유발시키게 되고 나아가 전자부품이 소진(Burnout)되는 직접적인 원인이 된다. 본 연구에서는 이러한 핵폭 방출 과도방사선에 대한 전자부품/장비의 내방사선관련 기초연구로 군전자부품의 감마-과도방사선에 대한 피해분석 시험을 수행하고 나아가 과도방사선 방호기술 체계구축의 필요성에 대해 논하였다. 과도펄스 방사선시험은 군용으로 분류된 반도체 칩을 대상으로 포항 전자빔가속기를 사용하였다. 핵폭발 방출 과도방사선을 모사하기 위해 감마선 변환장치를 MCNP 설계를 통해 제작하고 단일모드의 마이크로초 단위 감마펄스 방사선을 방출시켜 시험대상 칩을 부착한 시험보드에 조사하는 과정으로 실험을 진행하였다. 온라인 고속 측정장치를 통한 전자소자의 과도방사선시험에서 다양한 피해현상을 측정할 수 있었고, 열상카메라 촬영을 통하여 과열상태를 관측함으로써 피해현상의 검증과 더불어 소진현상으로의 전개 가능성을 확인하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.8
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• pp.898-907
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• 1992

This paper deals with a detailed analysis of CMOS latch up dependancies on the layout and geo-metrical demensions on the mask using same materials and same processes. For this purpose, six different layout models depending upon the N+ / P+ spacing and three different guard ring models have been gesigned, fabricated, and tested. As a result, common emitter current gain, shunt resistance, and holeing current versus N+/P+ spacing have been measured and analyzed experimentally. Also the fact that guard ring is sffective in reducing the latchup possibility has been verified through this study.