• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.163-166
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• 2003

The electrothermal simulation of high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) in thin Silicon on insulator (SOI) and Silicon on sapphire (SOS) for thermal conductivity and sink is performed by means of MEDICI. The finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on-insulator (SOI) devices. In this paper, using for SOI LIGBT, we simulated electrothermal for device that insulator layer with $SiO_2\;and\;Al_2O_3$ at before and after latch up to measured the thermal conductivity and temperature distribution of whole device and verified that SOI LIGBT with $Al_2O_3$ insulator had good thermal conductivity and reliability

• Journal of Power Electronics
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• v.9 no.3
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• pp.464-471
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• 2009

This paper introduces a new Motion-$SPM^{TM}$ (Smart Power Modules) module in Single In-line Package (SIP), which is a fully optimized intelligent integrated IGBT inverter module for up to 1kW low power motor drive applications. This module offers a sophisticated, integrated solution and tremendous design flexibility. It also takes advantage of pliability for the arrangement of heat-sink due to two types of lead forms. It comes to be realized by employing non-punch-through (NPT) IGBT with a fast recovery diode and highly integrated building block, which features built-in HVICs and a gate driver that offers more simplicity and compactness leading to reduced costs and high reliability of the entire system. This module also provides technical advantages such as the optimized cost effective thermal performances through IMS (Insulated Metal Substrate), the high latch immunity. This paper provides an overall description of the Motion-$SPM^{TM}$ in SIP as well as actual application issues such as electrical characteristics, thermal performance, circuit configurations and power ratings.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.10-17
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• 1999

In this paper, CMOS IADC(Current-mode Analog-to-Digital Converter) which consists of only CMOS transistors is proposed. Each stages is made up 1.5-bit bit cells composed of CSH(Current-mode Sample-and-Hold) and CCMP(Current Comparator). The differential CSH which designed to eliminate CFT(Clock Feedthrough), to meet at least 9-bit resolution, is placed at the front-end of each bit cells, and each stages of bit cell ADSC (Analog-to-Digital Subconverter) is made up two latch CCMPs. With the HYUNDAI TEX>$0.65\mu\textrm{m}$ CMOS parameter, the ACAD simulation results show that the proposed IADC can be operated with 47 dB of SINAD(Signal to Noise- Plus-Distortion), 50dB(8-bit) of SNR(Signal-to-Noise) and 37.7 mW of power consumption for input signal of 100 KHz at 20 Ms/s.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.291-296
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• 2015

This paper describes the design of a high-speed comparator for high-speed automatic test equipment (ATE). The normal comparator block, which compares the detected signal from the device under test (DUT) to the reference signal from an internal digital-to-analog converter (DAC), is composed of a rail-to-rail first pre-amplifier, a hysteresis amplifier, and a third pre-amplifier and latch for high-speed operation. The proposed continuous comparator handles high-frequency signals up to 800MHz and a wide range of input signals (0~5V). Also, to compare the differences of both common signals and differential signals between two DUTs, the proposed differential mode comparator exploits one differential difference amplifier (DDA) as a pre-amplifier in the comparator, while a conventional differential comparator uses three op-amps as a pre-amplifier. The chip was implemented with $0.18{\mu}m$ Bipolar CMOS DEMOS (BCDMOS) technology, can compare signal differences of 5mV, and operates in a frequency range up to 800MHz. The chip area is $0.514mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.105-112
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• 2009

In this paper, we investigated abnormal ESD failure on guard-rings in the smart power IC fabricated with $0.35{\mu}m$ Bipolar-CMOS-DMOS (BCD) technology. Initially, ESD failure occurred below 200 V in the Machine Model (MM) test due to current crowding in the parasitic diode associated with the guard-rings which are generally adopted to prevent latch-up in high voltage devices. Optical Beam Induced Resistance Charge (OBIRCH) and Scanning Electronic Microscope (SEM) were used to find the failure spot and 3-D TCAD was used to verify cause of failure. According to the simulation results, excessive current flows at the comer of the guard-ring isolated by Local Oxidation of Silicon (LOCOS) in the ESD event. Eventually, the ESD failure occurs at that comer of the guard-ring. The modified comer design of the guard-ring is proposed to resolve such ESD failure. The test chips designed by the proposed modification passed MM test over 200 V. Analyzing the test chips statistically, ESD immunity was increased over 20 % in MM mode test. In order to avoid such ESD failure, the automatic method to check the weak point in the guard-ring is also proposed by modifying the Design Rule Check (DRC) used in BCD technology. This DRC was used to check other similar products and 24 errors were found. After correcting the errors, the measured ESD level fulfilled the general industry specification such as HBM 2000 V and MM 200V.

• Journal of Astronomy and Space Sciences
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• v.29 no.3
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• pp.315-320
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• 2012

We developed a mass-memory chip by staking 1 Gbit double data rate 2 (DDR2) synchronous dynamic random access memory (SDRAM) memory core up to 4 Gbit storage for future satellite missions which require large storage for data collected during the mission execution. To investigate the resistance of the chip to the space radiation environment, we have performed heavy-ion-driven single event experiments using Heavy Ion Medical Accelerator in Chiba medium energy beam line. The radiation characteristics are presented for the DDR2 SDRAM (K4T1G164QE) fabricated in 56 nm technology. The statistical analyses and comparisons of the characteristics of chips fabricated with previous technologies are presented. The cross-section values for various single event categories were derived up to ~80 $MeVcm^2/mg$. Our comparison of the DDR2 SDRAM, which was fabricated in 56 nm technology node, with previous technologies, implies that the increased degree of integration causes the memory chip to become vulnerable to single-event functional interrupt, but resistant to single-event latch-up.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.5
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• pp.639-642
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• 2013

In this paper, proposed NED(nuclear event detectors) for detection of a transient radiation. Nuclear event detector was blocked of power temporary for defence of critical damage at a electric device when a induced transient radiation. Conventional NED consist of BJT, resistors and capacitors. The NED supply voltage of 5V and MCM(Multi Chip Module) structures. The proposed NED were designed for low supply voltage using 0.18um CMOS process. The response time of proposed NED was 34.8ns. In addition, pulse radiation experiments using a electron beam accelerator, the output signal has occurred.

• Journal of Satellite, Information and Communications
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• v.11 no.4
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• pp.21-26
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• 2016

The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different implant of channel blocking region was discussed for high voltage I/O applications. A conventional NSCR standard device shows low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified channel blocking structure demonstrate the improved ESD protection performance as a function of channel implant variation. Therefore, the channel blocking implant was a important parameter. Since the modified device with CPS_PDr+HNF structure satisfied the design window, we confirmed the applicable possibility as a ESD protection device for high voltage operating microchips.

• ETRI Journal
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• v.38 no.2
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• pp.272-279
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• 2016

In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) is proposed. The proposed new structure specifically for an AHHVSCR-based electrostatic discharge (ESD) protection circuit can protect integrated circuits from ESD stress. The new structure involves the insertion of a PMOS into an AHHVSCR so as to prevent a state of latch-up from occurring due to a low holding voltage. We use a TACD simulation to conduct a comparative analysis of three types of circuit - (i) an AHHVSCR-based ESD protection circuit having the proposed new structure (that is, a PMOS inserted into the AHHVSCR), (ii) a standard AHHVSCR-based ESD protection circuit, and (iii) a standard HHVSCR-based ESD protection circuit. A circuit having the proposed new structure is fabricated using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology. The fabricated circuit is also evaluated using Transmission-Line Pulse measurements to confirm its electrical characteristics, and human-body model and machine model tests are used to confirm its robustness. The fabricated circuit has a holding voltage of 18.78 V and a second breakdown current of more than 8 A.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.601-607
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• 2015

A set of novel silicon controlled rectifier (SCR) devices' characteristics have been analyzed and verified under the electrostatic discharge (ESD) stress. A ring-shaped diffusion was added to their anode or cathode in order to improve the holding voltage (Vh) of SCR structure by creating new current discharging path and decreasing the emitter injection efficiency (${\gamma}$) of parasitic Bipolar Junction Transistor (BJT). ESD current density distribution imitated by 2-dimensional (2D) TCAD simulation demonstrated that an additional current path exists in the proposed SCR. All the related devices were investigated and characterized based on transmission line pulse (TLP) test system in a standard $0.5-{\mu}m$ 24 V CDMOS process. The proposed SCR devices with ring-shaped anode (RASCR) and ring-shaped cathode (RCSCR) own higher Vh than that of Simple SCR (S_SCR). Especially, the Vh of RCSCR has been raised above 33 V. What's more, their holding current is kept over 800 mA, which makes it possible to design power clamp with SCR structure for on chip ESD protection and keep the protected chip away from latch-up risk.