• 한국세라믹학회지
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• 제45권9호
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• pp.561-566
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• 2008

Carbon fiber fabric-silicon carbide composites were fabricated by liquid silicon infiltration (LSI) process. The porous two-dimensional carbon fiber fabric performs were prepared by 13 plies of 2D-plain-weave fabric in a three laminating method, [0/90], [${\pm}45$], [$0/90/{\pm}45$] lay-up, respectively. Before laminating, a thin pyrolytic carbon (PyC) layer deposited on the surface of 2D-plain weave fabric sheets as interfacial layer with $C_3H_8$ and $N_2$ gas at $900^{\circ}C$. A densification of the preforms for $C_f-Si-SiC$ matrix composite was achieved according to the LSI process at $1650^{\circ}C$ for 30 min. in vacuum atmosphere. The bending strength of the each composite were measured and the microstructural consideration was performed by a FE-SEM.

• 한국재료학회지
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• 제34권2호
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• pp.111-115
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• 2024

Silicon carbide (SiC) has emerged as a promising material for next-generation power semiconductor materials, due to its high thermal conductivity and high critical electric field (~3 MV/cm) with a wide bandgap of 3.3 eV. This permits SiC devices to operate at lower on-resistance and higher breakdown voltage. However, to improve device performance, advanced research is still needed to reduce point defects in the SiC epitaxial layer. This work investigated the electrical characteristics and defect properties using DLTS analysis. Four deep level defects generated by the implantation process and during epitaxial layer growth were detected. Trap parameters such as energy level, capture-cross section, trap density were obtained from an Arrhenius plot. To investigate the impact of defects on the device, a 2D TCAD simulation was conducted using the same device structure, and the extracted defect parameters were added to confirm electrical characteristics. The degradation of device performance such as an increase in on-resistance by adding trap parameters was confirmed.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.31-33
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• 2002

Si TFTs are applied not only to stacked SRAM but also to FPD. Improvement of device characteristic such as an enhancement of carrier mobility or a reduction of leakage current is studied intensively. The TFT technology is developing based on conventional Si LSI technology. By establishing a stable fabrication process on flexible substrate and high performance characteristic uniformly and reliably, TFT technology has a possibility to develop to SOP or other highly functional applications similar to or beyond the conventional Si LSI in the era of information and telecommunication.

• 전자공학회논문지S
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• 제34S권2호
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• pp.79-93
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• 1997

This paper presents a linear shift-invariant system euqivalent to morphological dilation for a memoryless uniform source in the sense of the power spectral density function, and comares it with dialtion. This equivalent LSI system is found through spectral decomposition and, for dilation and with windwo size L, it is shown to be a finite impulse response filter composed of L-1 delays, L multipliers and three adders. Th ecoefficients of the equivalent systems are tabulated. The comparisons of dilation and its equivalent LSI system show that probability density functions of the output sequences of the two systems are quite different. In particular, the probability density functon from dilation of an independent and identically distributed uniform source over the unit interval (0, 1) shows heavy probability in around 1, while that from the equivalent LSI system shows probability concentration around themean vlaue and symmetricity about it. This difference is due to the fact that dilation is a non-linear process while the equivalent system is linear and shift-ivariant. In the case that dikation is fabored over LSI filters in subjective perforance tests, one of the factors can be traced to this difference in the probability distribution.

• 한국정보통신학회논문지
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• 제9권3호
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• pp.582-586
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• 2005

본 논문은 locking 상태에 따라서 루프대역폭이 변화하는 Phase Locked Loop (PLL)의 구조를 제안하였다. 제안한 PLL은 기본적인 PLL 블록과 NOR Gate, Inverter, Capacitor, 그리고 Schmitt trigger로 이루어진 Locking Status Indicator(LSI) 블록으로 구성되었다. LSI는 Loop Fille.(LF)에 공급되는 전류와 저항 값을 locking 상태에 따라 변화시켜서 unlock이 되면 넓은 루프대역폭 가지는 PLL로, lock이 되면 좁은 루프대역폭을 가지는 PLL로 동작하도록 한다. 이러한 구조의 PLL은 짧은 locking 시간과 저 잡음의 특성을 동시에 만족시킬 수 있다. 제안된 PLL은 Hynix CMOS $0.35{\mu}m$ 공정으로 Hspice 시뮬레이션 하였으며 40us의 짧은 locking 시간과 -76.1dBc 크기의 spur를 가진다.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 2007년도 춘계학술대회 학술발표 논문집 제17권 제1호
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• pp.485-488
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• 2007

최근 Analog Sampled-Data 신호처리를 위하여 주목되고 있는 SI(Switched-Current) circuit은 저전력 동작을 하는 장점이 있지만, 반면에 SI circuit에서의 기본 회로인 Current Memory는 Charge Injection에 의한 Clock Feedthrough이라는 치명적인 단점을 갖고 있다. 따라서 본 논문에서는 Current Memory의 문제점인 Clock Feedthrough의 일반적인 해결방안으로 Dummy Switch의 연결을 검토하였고, Austria Mikro Systeme(AMS)에서 $0.35{\mu}m$ CMOS process BSIM3 Model로 제작하기 위하여 Current Memory의 Switch MOS와 Dummy Switch MOS의 적절한 Width을 정의하여야 하므로, 그 값을 도출하였다. Simulation 결과, Switch의 Width는 $2{\mu}m$, Dummy Switch의 Width는 $2.35{\mu}m$로 정의될 수 있음을 확인하였다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2017년도 춘계학술대회
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• pp.691-693
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• 2017

본 논문에서는 시간 차 감지기와 LSI(Lock Status Indicator)를 사용하여 빠른 위상고정 시간을 갖는 위상고정루프를 제안하였다. 제안된 위상고정루프는 1.8V $0.18{\mu}m$ CMOS 공정을 사용하여 설계하였고, Hspice 시뮬레이션을 통해 회로의 동작을 검증하였다.다음은 요약문입니다.

• 전자진흥
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• 제3권6호
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• pp.98-111
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• 1983

• 한국표면공학회지
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• 제32권3호
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• pp.289-296
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• 1999

The integration of the LSI has been greatly improved and the circuit patters on the LSI are becoming finer line and pitch. The high-density electronic packaging technology is improved. In order to realize the high-density packaging technology, the density of the circuit wiring of the printed circuit boards have also been more dense. The build-up process multilayer printed circuit board technology have a lot of vias, possibilities of the finer conductor wirings and have a freedom of capabilities of wiring design. The build-up process printed circuit boards have the wiring rules which are the pattern width: $100-20\mu\textrm{m}$, the via hole diameter: $100-50\mu\textrm{m}$. There three kinds of build-up processes as far materials and hole drilling. In this paper, the recent technology trends of the build-up printed circuit board technologies are described.

• 한국추진공학회지
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• 제26권6호
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• pp.21-27
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• 2022

C_f/SiC 복합재는 저밀도, 높은 기계적 강도, 우수한 열 안정성을 가지고 있어 로켓 추진기관, 항공 및 군사 분야 등의 고온 응용 산업에 유망한 재료이다. 그러나 용융 실리콘 함침(Liquid Silicon Infiltration, LSI) 공정을 통해 제작된 복합재는 잔존하는 Si에 의하여 물리적, 열적 특성이 저하된다. 본 논문에서는 LSI 공정을 통해 제작된 C_f/SiC 복합재의 내부 Si을 제거하기 위한 방안으로 탈규소화(de-siliconization) 공정을 도입하였다. 최대 5분 동안 옥시아세틸렌 토치 테스트를 진행하고 시편의 산화된 표면과 단면은 3D scanning, X-ray diffraction(XRD), 광학현미경(OM), 전자주사현미경(SEM)으로 분석하였다.