Korean Journal of Materials Research (한국재료학회지)

Materials Research Society of Korea (한국재료학회)
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Analysis of Electrical Characteristics due to Deep Level Defects in 4H-SiC PiN Diodes

4H-SiC PiN 다이오드의 깊은 준위 결함에 따른 전기적 특성 분석

  • Tae-Hee Lee (Department of Electronic Materials Engineering, Kwangwoon University) ;
  • Se-Rim Park (Department of Electronic Materials Engineering, Kwangwoon University) ;
  • Ye-Jin Kim (Department of Electronic Materials Engineering, Kwangwoon University) ;
  • Seung-Hyun Park (Department of Electronic Materials Engineering, Kwangwoon University) ;
  • Il Ryong Kim (Technology Team, System LSI, SAMSUNG ELECTRONICS) ;
  • Min Kyu Kim (Technology Team, System LSI, SAMSUNG ELECTRONICS) ;
  • Byeong Cheol Lim (Technology Team, System LSI, SAMSUNG ELECTRONICS) ;
  • Sang-Mo Koo (Department of Electronic Materials Engineering, Kwangwoon University)
  • 이태희 (광운대학교 전자재료공학과) ;
  • 박세림 (광운대학교 전자재료공학과) ;
  • 김예진 (광운대학교 전자재료공학과) ;
  • 박승현 (광운대학교 전자재료공학과) ;
  • 김일룡 (삼성전자 System LSI사업부 제품기술팀) ;
  • 김민규 (삼성전자 System LSI사업부 제품기술팀) ;
  • 임병철 (삼성전자 System LSI사업부 제품기술팀) ;
  • 구상모 (광운대학교 전자재료공학과)
  • Received : 2024.01.22
  • Accepted : 2024.02.15
  • Published : 2024.02.27
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Abstract

Silicon carbide (SiC) has emerged as a promising material for next-generation power semiconductor materials, due to its high thermal conductivity and high critical electric field (~3 MV/cm) with a wide bandgap of 3.3 eV. This permits SiC devices to operate at lower on-resistance and higher breakdown voltage. However, to improve device performance, advanced research is still needed to reduce point defects in the SiC epitaxial layer. This work investigated the electrical characteristics and defect properties using DLTS analysis. Four deep level defects generated by the implantation process and during epitaxial layer growth were detected. Trap parameters such as energy level, capture-cross section, trap density were obtained from an Arrhenius plot. To investigate the impact of defects on the device, a 2D TCAD simulation was conducted using the same device structure, and the extracted defect parameters were added to confirm electrical characteristics. The degradation of device performance such as an increase in on-resistance by adding trap parameters was confirmed.

Keywords

Acknowledgement

The present research has been conducted by the Excellent researcher support project of Kwangwoon University in 20 23 and the Samsung Electronics Co., Ltd. (IO230112-04602-01), and the Korea Institute for Advancement of Technology (KIAT) (P0012451).

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