• Title/Summary/Keyword: LSI

Search Result 354, Processing Time 0.026 seconds

Proposal of Framing System Realization for Synchronization Stability Improvement (동기 안정도 개선을 위한 동기 시스템 장치화의 제안)

  • Lim, Joung-Suk;Yeom, Heung-Yeol;Chang, Dae-Ig;Rhee, Man-Young
    • Proceedings of the KIEE Conference
    • /
    • 1988.07a
    • /
    • pp.161-164
    • /
    • 1988
  • The purpose of this paper is to propose a simple firmware realization of PCM framing system, which exploits LSI memories for performance improvement and hardware simplification. The proposed system simply consists of a tapped delay line for simultaneous observation of in framing-bits and ROM programmed sequence controller for framing process. Perpormance analyses are made in terms of misframe interval, sync-loss-detection time and reframe time. The proposed strategy proved to be significantly better in reframe time, stability and hardware implementation.

  • PDF

Analysis of electron transport characteristic in He gas by MCS (MCS에 의한 Helium 기체 중의 전자수송특성 해석)

  • Song, Byoung-Doo;Ha, Sung-Chul;Seo, Sang-Hyoen;Moon, Ki-Seok;Yoo, Hoy-Young;Kim, Sang-Nam
    • Proceedings of the KIEE Conference
    • /
    • 1998.07e
    • /
    • pp.1752-1754
    • /
    • 1998
  • Recently the research about electron transport characteristic and energy distribute function in mixture gases within Helium, has been used and developed widely as industrial quality improvement of extinguish characteristic, electrical dielectric strength ability of application of each species high voltage apparatus, gas plasma etching progress of work to use manufacture of semiconductor, thin film molding by CVD, insulation film to use ultra LSI, etc. This paper analyze electron transport characteristic in the range E/N $1{\sim}60$[Td], pressure $0.1{\sim}6.0$[Torr] by MCS. It is necessary to seek electron drift velocity, diffusion coefficient, lonization coefficients, characteristic energy, mean energy and electron energy distribution function as electron transport characteristic.

  • PDF

Brazing기술의 기초와 실제 I

  • 강정윤;김우열
    • Journal of Welding and Joining
    • /
    • v.10 no.2
    • /
    • pp.11-18
    • /
    • 1992
  • (Brazing)에 의한 금속의 접합기술은 이미 BC 3000년경 고대 바빌로니아(Babylonia)에서 귀금 속의 장식품을 만드는데 에 이용되어져 왔다. 근대에 와서는 1950년 후반 N.Redns등의 탄소강의 Ag브레이징을 개발한 이후부터 브레이징에 관한 연구가 활발하게 되었다. 즉, 삽입금속 및 플 락스의 개발, 삽입금속과 모재의 젖음성, 브레이징의 강열법과 분위기 조절, 접합이음부의 설계 등에 대해서 계통적인 연구가 시도되었다. 그 결과, 최근에 이르러서는 스테인레스 파이프의 금브레이징에 의한 로켓트부스타(Rocket Booster)의 제작, LSI의 프린터배선, 파인 세라믹스와 금속을 브레이징하여 소형 자동차의 Turbo Charger Rotar의 제작등에 이용되고 있고, 첨단기 술에 없어서는 안될 중요한 접합기술로 주목을 받고 있다. 선진국에서는 많은 연구 개발의 성 과로 고부가가치 제품의 생산에 활용되고 있지만, 현재 국내에서는 1950년대의 기술수준에 있고, 연구 개발에 대한 업계 및 학계의 관심의 부족하기 때문에 기술축적은 전혀 되어 있지 않다. 특히, Brazing에 관련된 자료나 기초지식을 습득하기 위한 교재도 출판된 것이 없고, 번역된 전문 서적도 구하기가 힘들기 때문에 브레이징 기술에 대한 인식도 낮고, 적재적소에 활용도 되지 않고 있는 실정이다. 이와 같은 배경 하에서 저자들은 브레이징에 대해서 관심을 가지는 회원 들에게 조금이나마 도움을 주고자 외국에서 출판된 서적 및 논문 등을 참고로 하여 정리하여 브레이징의 기초와 실제라는 제목으로 4회에 걸쳐서 게재하고자 한다.

  • PDF

On-time Production and Delivery Improvements through the Demand-Lot Pegging Framework for a Semiconductor Business (반도체 산업에서 생산용량을 고려한 오더-로트 페깅기반의 납기약속 방법의 정합성 향상에 대한 연구)

  • Seo, Jeong-Cheol;Bang, June-Young
    • Journal of Korean Society of Industrial and Systems Engineering
    • /
    • v.37 no.4
    • /
    • pp.126-133
    • /
    • 2014
  • This paper addresses order-lot pegging issues in the supply chain of a semiconductor business. In such a semiconductor business (memory or system LSI) order-lot pegging issues are critical to achieving the goal of ATP (Available to Promise) and on-time production and delivery. However existing pegging system and researches do not consider capacity limit on bottleneck steps. This paper presents an order-lot pegging algorithm for assigning a lot to an order considering quality constraints of each lot and capacity of bottleneck steps along the entire FAB. As a result, a quick and accurate response can be provided to customer order enquiries and pegged lot lists for each promised orders can be shown transparently and short or late orders can be detected before fixing the order.

Linear Corrector Overcoming Minimum Distance Limitation for Secure TRNG from (17, 9, 5) Quadratic Residue Code

  • Kim, Young-Sik;Jang, Ji-Woong;Lim, Dae-Woon
    • ETRI Journal
    • /
    • v.32 no.1
    • /
    • pp.93-101
    • /
    • 2010
  • A true random number generator (TRNG) is widely used to generate secure random numbers for encryption, digital signatures, authentication, and so on in crypto-systems. Since TRNG is vulnerable to environmental changes, a deterministic function is normally used to reduce bias and improve the statistical properties of the TRNG output. In this paper, we propose a linear corrector for secure TRNG. The performance of a linear corrector is bounded by the minimum distance of the corresponding linear error correcting code. However, we show that it is possible to construct a linear corrector overcoming the minimum distance limitation. The proposed linear corrector shows better performance in terms of removing bias in that it can enlarge the acceptable bias range of the raw TRNG output. Moreover, it is possible to efficiently implement this linear corrector using only XOR gates, which must have a suitable hardware size for embedded security systems.

Efficient Block Packing to Minimize Wire Length and Area

  • Harashima, Katsumi;Ootaki, Yousuke;Kutsuwa, Toshirou
    • Proceedings of the IEEK Conference
    • /
    • 2002.07c
    • /
    • pp.1539-1542
    • /
    • 2002
  • In layout of LSI and PWB, block pack- ing problem is very important in order to reduce chip area. Sequence-pair is typical one of conventional pack- ing method and can search nearly-optimal solution by using Simulated Annealing(SA). SA takes huge computation time due to evaluating of various packing results. Therefore, Sequence-pair is not effective enough for fast layout evaluation including estimation of wire length and rotation of every blocks. This paper proposes an efficient block packing method to minimize wire length and chip area. Our method searches an optimal packing efficient- ly by using a cluster growth algorithm with changing the most valuable packing score on packing process.

  • PDF

디지털 방송의 현황과 과제

  • 대한전기협회
    • JOURNAL OF ELECTRICAL WORLD
    • /
    • s.265
    • /
    • pp.72-81
    • /
    • 1999
  • 방송의 디지털화가 실현되면서 다가오는 21세기는 새로운 방송문화의 창조가 기대된다. 디지털방송은 인프라스트럭처에서 서비스에 이르는 미디어의 변혁이며, 세계적인 규모로서 특히 지역의 구석구석까지 풍요로운 사회생활을 기대할 수 있을 것이다. 이를 보급하기 위해서는 각국의 시책, 인프라의 정비, 기술규격의 표준화, 값싼 고기능 정보단말, 매력적인 서비스를 동시에 병행하여 유저에게 받아들여질 수 있는 프로세스를 창출하는 것이 필요하다. 디지털방송의 전개는 영상$\cdot$음성부호화 기술의 규격표준화를 계기로 위성$\cdot$지상파$\cdot$케이블의 각 전송매체에서 시작하여 현장감이 넘치는 고품질 텔레비전, 다채널, 멀티미디어정보서비스의 실현을 위해 일본$\cdot$미국$\cdot$유럽 각국에서 동시에 활발하게 추진중에 있다. 이와같은 디지털방송서비스를 실현하는데는 오디오 비쥬얼기술과 통신 및 컴퓨터를 융합한 고도의 기술개발이 필요하다. 미쓰비시전기(이하''동사''라 한다)는 새로운 시대를 열기 위하여 방송국시스템, 집배신네트워크, 가정용수신기, 디지털텔레비전용 CODEC, 기간 LSI 등의 개발에 적극적으로 대처하고 있다.

  • PDF

A System-on-a-Chip Design for Digital TV

  • Rhee, Seung-Hyeon;Lee, Hun-Cheol;Kim, Sang-Hoon;Choi, Byung-Tae;Lee, Seok-Soo;Choi, Seung-Jong
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.5 no.4
    • /
    • pp.249-254
    • /
    • 2005
  • This paper presents a system-on-a-chip (SOC) design for digital TV. The single LSI incorporates almost all essential parts such as CPU, ISO/IEC 11172/13818 system/audio/video decoders, a video post-processor, a graphics/OSD processor and a display processor. It has analog IP's inside such as video DACs, an audio PLL, and a system PLL to reduce the system-level implementation cost. Descramblers and Smart Card interface are included to support widely used conditional access systems. The video decoder can decode two video streams simultaneously. The DSP-based audio decoder can process various audio coding specifications. The functional blocks for video quality enhancement also form outstanding features of this SoC. The SoC supports world-wide major DTV services including ATSC, ARIB, DVB, and DIRECTV.

Control of Elevator System Model Using Microcomputer (Microcomputer를 이용한 엘리베이터 시스템 모델의 제어)

  • 송현빈;변증남
    • Journal of the Korean Institute of Telematics and Electronics
    • /
    • v.16 no.2
    • /
    • pp.35-42
    • /
    • 1979
  • A conventional elevator system, which requires simultaneous control of the speed and the position, contains complicated analog hardwares as the control system. Recent advances in LSI technology, however, suggest that the control of such ane levator system may be realized by Incorporating digital device and microcomputer. In this paper, such a possibility is investigated. In this paper, the digital controller, witch is implemented around an IMSAl 8080 microcomputer is designed for the control of model elevator system. Experiments show that this contra .system tracks the given velocity curve as well as it brings the elevator to the enact point.

  • PDF

70nm CMOS BSIM4 Macro modeling for RFIC design (RFIC설계를 위한 70nm CMOS의 BSIM4 매크로 모델링)

  • Choi, Gil-Bok;Baek, Rock-Hyun;Kang, Hee-Sung;Jeong, Yoon-Ha
    • Proceedings of the IEEK Conference
    • /
    • 2006.06a
    • /
    • pp.613-614
    • /
    • 2006
  • In this paper, BSIM4's IIR(Intrinsic Input Resistance) model that has a difficulty to predict $Z_{11}$ exactly is investigated by analyzing S-parameter measurement. Then a BSIM4 macro model for 70nm RF MOSFETs is proposed. That model uses external effective gate resistance which is composed of R and parallel RC. Comparison between simulation results using proposed model and IIR model is shown. The proposed model shows a better agreement between measured and simulated results up to 20GHz.

  • PDF