• The Korean Journal of Ceramics
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• v.1 no.2
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• pp.96-100
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• 1995

Recently, alumina/glass composites have been applied as a substrate material for hybrid IC and LSI multi-chip packaging. In this study, the characterization of sodium borosilicate glasses containing NaF and $AlF_3$ and the preparation of the resulted glass/alumina composites have been examined and the effect of the addition of fluorides on the thermal. and dielectric properties of the sintered composites have been studied. The sintering temperature of specimens was lowered by about 100-$150^{\circ}C$ by the addition of fluorine compared with the specimens without fluorine. The specimens containing fluorine showed slightly lower dielectric constants than those of the specimens without fluorine.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.11
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• pp.2850-2861
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• 1996

This paper describes the design of AATM switch LIS of shared buffer type with linked-list architecture to control memory access. The proposed switch LSI consists of the buffer memory, controller and FIFO memory blocks and two special circuits to avoid the cell blocking. One of the special circuit is a new address control scheme with linked-list architecture which maintains the address of buffer memory serially ordered from write address to read address. All of the address is linked as chain is operated like a FIFO. The other is slip-flag register it will be hold the address chain when readaddress missed the reading of data. The circuits control the buffer memory efficiently and reduce the cell loss rate. As a result the designed chip operates at 33ns and occupied on 2.7*2.8mm$^{2}$ using 0.8.mu.m CMOS technology.

• Electrical & Electronic Materials
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• v.3 no.2
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• pp.123-130
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• 1990

본 논문은 페라이트의 온도특성을 측정하기 위한 다중측정시스템의 설계에 관하여 연구한 것이다. 본 시스템은 전기로의 온도를 제어하기 위한 열전대 콘트롤러, 릴레이 동작을 제어하기 위한 릴레이 콘트롤러 및 릴레이를 구동시키기 위한 스윗칭부, 그리고 GPIB를 이용한 LCR메터 제어부와 이들을 마이크로 컴퓨터와 통신하기 버스 라인으로 구성하였다. 열전대 콘트롤러와 릴레이 콘트롤러는 8255A(Intel LSI)를 주로 이용하여 설계하였으며 릴레이로는 고주파용 릴레이를 사용하여 스윗칭 트랜지스터로 구동시키는 방법을 택하였다. 그리고 LCR-메터에는 GPIB(AD50488)보드를 사용하였다. 측정시료로서는 복합첨가제방식에 의하여 제작된 Mn-Zn-Fe계 페라이트의 시편을 사용하였으며 시료의 특성측정은 자체 제작한 자동계측시스템을 이용하여 분석하였다. 측정결과 온도보상점 T$_{o}$ 와 큐리온도 T$_{c}$ 바로 아래에서 투자율의 급격한 변화를 확인할 수 있었다. 그리고 특성의 계측에 있어서 일관성이 있고 정확한 자료를 얻을 수 있었으며 따라서 본 시스템이 인터페이스와 컴퓨터 사이의 연결성이 좋은 자동다중계측시스템으로 활용 할 수 있음을 확인한다.

• Transactions on Electrical and Electronic Materials
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• v.11 no.5
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• pp.234-237
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• 2010

Nanoenergetic materials were synthesized and the thermite reaction between the CuO nanowires and the deposited nano-Al by Joule heating was studied. CuO nanowires were grown by thermal annealing on a glass substrate. To produce nanoenergetic materials, nano-Al was deposited on the top surface of CuO nanowires. The temperature of the first exothermic reaction peak occurred at approximately $600^{\circ}C$. The released heat energy calculated from the first exothermic reaction peak in differential scanning calorimetry, was approximately 1,178 J/g. The combustion of the nanoenergetic materials resulted in a bright flash of light with an adiabatic frame temperature potentially greater than $2,000^{\circ}C$. This thermite reaction might be utilized to achieve a highly reliable selective area crystallization of amorphous silicon films.

• Proceedings of the Korea Concrete Institute Conference
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• 1993.10a
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• pp.207-212
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• 1993

When constructing highly precise production plants, for example, super LSI plants or semiconductor plants, it is important to take the necessary control countermeasures into consideration to obtain the working microvibration environment, which is directly related to product precision. Working environment of a clean room means vibration-free and there are only ultra-miro vibration which human cannot sense. In order to provide an place having a vibration-free working environment with only ultra-micro vibration it is necessary to posses a great number of vibration isolation technlogies, wide-ranging and abundant survey and teat data, and a high level of knowledge enabling comprehensive judgments to be made. In this study, experimental modal analysis is used to analyze the dynamic characteristics of double floor for vibration-proofing near apparatus which generate vibration. It is concluded that the double floor system with rubber pad inserted between floor panel and pedestal is good for vibration proof.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1187-1188
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• 2008

An area of research called evolvable hardware has recently emerged which combines aspects of evolutionary computation with hardware design and synthesis. Evolvable hardware (EHW) is hardware that can change its own circuit structure by genetic learning to achieve maximum adaptation to the environment. In conventional EHW, the learning is executed by software on a computer. In this paper, we have studied and surveyed a gate-level evolvable hardware chip, by integrating both GA hardware and reconfigurable hardware within a single LSI chip. The chip consists of genetic algorithm(GA) hardware, reconfigurable hardware logic, and the control logic. In this paper, we describe the architecture, functions of the chip.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.81-88
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• 2002

A new pattern generator of BIST based on the pattern clustering is developed. The proposed technique embeds a pre-computed deterministic test set with low hardware overhead for test-per-clock environments. The test control logic is simple and can be synthesized automatically. Experimental results for the ISCAS benchmark circuits show that the effectiveness of the new pattern generator compared to the previous methods.

• Journal of electromagnetic engineering and science
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• v.15 no.4
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• pp.258-265
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• 2015

A de-embedding method for multiport networks, especially for coupled odd interconnection lines, is presented in this paper. This method does not require a conversion from S-parameters to T-parameters, which is widely used in the de-embedding technique of multiport networks based on cascaded simple two-port relations, whereas here, we apply an operation to the S-matrix to generate all the uncoupled and coupled coefficients. The derivation of the method is based on the relations of incident and reflected waves between the input of the entire network and the input of the intrinsic device under test (DUT). The characteristics of the intrinsic DUT are eventually achieved and expressed as a function of the S-parameters of the whole network, which are easily obtained. The derived coefficients constitute ABCD-parameters for a convenient implementation of the method into cascaded multiport networks. A validation was performed based on a spice-like circuit simulator, and this verified the proposed method for both uncoupled and coupled cases.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10b
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• pp.130-134
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• 1992

The ability of a robot system to comply to an environment via the control of tool-environment interaction force is of vital for the successful task accomplishment in many robot application. This paper presents the implementation of external force control for two dimensional contour following task using a commercial robot system. Force accommodation is used since a constraint imposed in our work is not to modify the commercial robot system. A linear, decoupled model of two dimensional contour following system in the discrete time domain is derived first. Then the experimental verification of linear control is obtained using a PUMA 560 manipulator with standard Unimation controller, Astek FS6-120A six axis wrist force sensor attached externally to the arm and LSI-11173 microcomputer. Experimentally obtained data shows that the RMS contact force error is 0.8246 N when following the straight edge and 2.3768 N when following 40 mm radius curved contour.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.75-79
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• 2009

A system-on-a-chip communication architecture has a significant impact on the performance and power consumption of modern multi-processors system-on-chips (MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus, system designers need tools to rapidly explore and evaluate communication architectures. In this paper we present the method for application-specific low-power bus architecture synthesis at system-level. Our paper has two contributions. First, we build a bus power model of AMBA AXI bus communication architecture. Second, we incorporate this power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the target bus architecture. The proposed exploration algorithm reduces power consumption by 20.1% compared to a maximally connected reduced matrix, and the area is also reduced by 20.2% compared to the maximally connected reduced matrix.