• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.3
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• pp.1051-1077
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• 2021

The secure communication of information is a major concern over the internet. The information must be protected before transmitting over a communication channel to avoid security violations. In this paper, a new hybrid method called compressed encrypted data embedding (CEDE) is proposed. In CEDE, the secret information is first compressed with Lempel Ziv Welch (LZW) compression algorithm. Then, the compressed secret information is encrypted using the Advanced Encryption Standard (AES) symmetric block cipher. In the last step, the encrypted information is embedded into an image of size 512 × 512 pixels by using image steganography. In the steganographic technique, the compressed and encrypted secret data bits are divided into pairs of two bits and pixels of the cover image are also arranged in four pairs. The four pairs of secret data are compared with the respective four pairs of each cover pixel which leads to sixteen possibilities of matching in between secret data pairs and pairs of cover pixels. The least significant bits (LSBs) of current and imminent pixels are modified according to the matching case number. The proposed technique provides double-folded security and the results show that stego image carries a high capacity of secret data with adequate peak signal to noise ratio (PSNR) and lower mean square error (MSE) when compared with existing methods in the literature.

• Journal of Information Processing Systems
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• v.13 no.2
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• pp.385-399
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• 2017

Nowadays, with the development of signal processing technique, the protection to the integrity and authenticity of images has become a topic of great concern. A blind image authentication technology with high tamper detection accuracy for different common attacks is urgently needed. In this paper, an improved fragile watermarking method based on local binary pattern (LBP) is presented for blind tamper location in images. In this method, a binary watermark is generated by LBP operator which is often utilized in face identification and texture analysis. In order to guarantee the safety of the proposed algorithm, Arnold transform and logistic map are used to scramble the authentication watermark. Then, the least significant bits (LSBs) of original pixels are substituted by the encrypted watermark. Since the authentication data is constructed from the image itself, no original image is needed in tamper detection. The LBP map of watermarked image is compared to the extracted authentication data to determine whether it is tampered or not. In comparison with other state-of-the-art schemes, various experiments prove that the proposed algorithm achieves better performance in forgery detection and location for baleful attacks.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.4
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• pp.39-47
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• 2004

In general, the steganographic algorithm for embedding message in JPEG images, such as Jsteg$^{(1)}$ , JP Hide ＆ Seek$^{(2)}$ , F5$^{(3)}$ , outGuess$^{(4)}$ replaces the LSB of DCT coefficients by the message bits. Both Jsteg and n Hide ＆ seek are detected by $\chi$$^2$- test, steganalytic technique$^{(4)}$ , the rate of detection is very low, though. In this Paper, we Propose a new steganalysis method that determine not only the existence of hidden messages in JPEG images exactly, but also the steganographic algorithm used. This method is advanced from the technique Blockiness$^{(5)}$ . It has many advantages that include a computational efficiency, correctness and that can detect without bowing steganographic algorithm. Experiment results show the superiority of our approach over Blockiness$^{(5)}$ .

• Journal of Broadcast Engineering
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• v.22 no.3
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• pp.350-365
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• 2017

Steganography is a technique for secret data communication, which is not perceived by third person between a receiver and a transmitter. It has been developed for thousands of years for the transmission of military, diplomatic or business information. The development of digital media and communication has led to the development of steganography techniques in modern times. Technic of image steganography include the LSB, which fixes the number of embedded bits into a pixel, and PVD, which exploits the difference value in the neighboring pixel pairs. In the case of PVD image steganography, a large amount of information is embedded fluidly by difference value in neighboring pixel pairs and the designed range table. However, since the secret information in order is embedded, if an error of the number of embedded bits occurs in a certain pixel pair, all subsequent information will be destroyed. In this paper, we proposes the method, which improve the vulnerability of PVD property about external attack or various noise and extract secret information. Experimental process is comparison analysis about stego-image, which embedded various noise. PVD shows that it is not possible to preserve secret information at all about noise, but it was possible to robustly extract secret information for partial noise of stego-image in case of the proposed PVD image steganography with locally-fixed number of embedding bits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.1-10
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• 2006

In this paper, an 1.8V 8-bit 500MSPS CMOS A/D Converter is proposed. In order to obtain the resolution of 8bits and high-speed operation, a Cascaded-Folding Cascaded-Interpolation type architecture is chosen. For the purpose of improving SNR, Cascaded-folding Cascaded-interpolation technique, distributed track and hold are included [1]. A novel folding circuit, a novel Digital Encoder, a circuit to reduce the Reference Fluctuation are proposed. The chip has been fabricated with a $0.18{\mu}m$ 1-poly 5-metal n-well CMOS technology. The effective chip area is $1050{\mu}m{\times}820{\mu}m$ and it dissipates about 146mW at 1.8V power supply. The INL and DNL are within ${\pm}1LSB$, respectively. The SNDR is about 43.72dB at 500MHz sampling frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.53-61
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• 2006

In high speed flash type or pipelining type A/D Converter, the faster sampling frequency is, the more the effect of DC reference fluctuation is increased by clock feed-through and kick-back. When we measure A/D Converter, further, external noise increases reference voltage fluctuation. Thus reference fluctuation reduction circuit must be needed in high speed A/D converter. Conventional circuit simply uses capacitor but layout area is large and it's not efficient. In this paper, a reference fluctuation reduction circuit using transmission gate is proposed. In order to verify the proposed technique, we designed and manufactured 6bit 2GSPS CMOS A/D converter. The A/D converter is based on 0.18um 1-poly 5-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply. It occupies chip area of $977um\times1040um$. Experimental result shows that SNDR is 36.25 dB and INL/DNL ${\pm}0.5LSB$ when sampling frequency is 2GHz.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.1
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• pp.96-102
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• 2009

Due to the rapid growth of the Internet, it is possible to distribute the digital content efficiently. However, the need for image data protection and secret communication technique is also on the rise because of an infringement of the copyright by malicious attackers. Shamir and Lin-Tsai proposed simple secret image encryption algorithms based on the principle of secret sharing, respectively. However, their secret sharing schemes have a serious problem which can be declined the image quality and it is possible for third party to know embed information. In this paper, we propose a new secret sharing scheme using gray code that can be increased the image quality and security. As a result of our experiment, the proposed scheme is not only shown of good image quality and but also provide enhanced security compare with Shamir and Lin-Tasi's schemes.