• Title/Summary/Keyword: LNA-Mixer

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A RF Frong-End CMOS Transceiver for 2㎓ Dual-Band Applications

  • Youn, Yong-Sik;Kim, Nam-Soo;Chang, Jae-Hong;Lee, Young-Jae;Yu, Hyun-Kyu
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.2 no.2
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    • pp.147-155
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    • 2002
  • This paper describes RF front-end transceiver chipset for the dual-mode operation of PCS-Korea and IMT-2000. The transceiver chipset has been implemented in a $0.25\mutextrm{m}$ single-poly five-metal CMOS technology. The receiver IC consists of a LNA and a down-mixer, and the transmitter IC integrates an up-mixer. Measurements show that the transceiver chipset covers the wide RF range from 1.8GHz for PCS-Korea to 2.1GHz for IMT-2000. The LNA has 2.8~3.1dB NF, 14~13dB gain and 5~4dBm IIP3. The down mixer has 15.5~16.0dB NF, 15~13dB power conversion gain and 2~0dBm IIP3. The up mixer has 0~2dB power conversion gain and 6~3dBm OIP3. With a single 3.0V power supply, the LNA, down-mixer, and up-mixer consume 6mA, 30mA, and 25mA, respectively.

A $0.5{\mu}m$ CMOS FM Radio Receiver For Zero-Crossing Demodulator (Zero-Crossing 복조기를 위한 $0.5{\mu}m$ CMOS FM 라디오 수신기)

  • Kim, Sung-Woong;Kim, Young-Sik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.2
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    • pp.100-105
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    • 2010
  • In this paper, a FM radio receiver integrated circuit has been developed based on $0.5{\mu}m$ CMOS process for Zero-Crossing FM demodulator over the 88MHz to 108MHz band. The receiver is designed with the low-IF architecture, and includes Low Noise Amplifier(LNA), Down-Conversion Mixer, Phase Locked Loop(PLL), IF LPF, and a comparator. The measured results of the LNA and Mixer show that the conversion gain of 23.2 dB, the input PldB of -14 dBm, and the noise figure of 15 dB. The measured analog block of the LPF and comparator show the voltage gain of over 89 dB, and the IF LPF can configure the passband from 600KHz to 1.3MHz with 100KHz step through the internal control register banks. The designed FM radio receiver operates at 4.5V with the total current consumption of 15.3mA, so the total power consumption is about 68.85mW. The commercial FM radio has been successfully received.

A Design of Low Frequency Noise Figure Improvement of RF Circuit for Direct Conversion Receiver (직접 변환 방식의 저주파 잡음 특성 개선을 위한 RF 전치부 설계 연구)

  • Choi, Hyuk-Jae;Choi, Jin-Kyu;Kim, Tae-Seong;Park, Do-Hyeon;Kim, Hyeong-Seok
    • 한국정보통신설비학회:학술대회논문집
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    • 2009.08a
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    • pp.305-308
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    • 2009
  • This paper presents the design and analysis of RF Front End for Wireless Heartbeat measurement System. In this work LNA, an inductor connected at the gate of the cascode transistor and capacitive cross-coupling are strategically combined to reduce the noise and the nonlinearity influences of the cascode transistors in a differential LNA. The Mixer is implemented by using the Gilbert-type configuration, cross pmos injection technique and the resonating technique for the tail capacitance. The resulting LNA achieves 1.26 dB NF, better than 1.88dB NF Typical Also Mixer resulting achieves 9.8dB at 100KHz.

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E-Band Wideband MMIC Receiver Using 0.1 ${\mu}m$ GaAs pHEMT Process

  • Kim, Bong-Su;Byun, Woo-Jin;Kang, Min-Soo;Kim, Kwang Seon
    • ETRI Journal
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    • v.34 no.4
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    • pp.485-491
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    • 2012
  • In this paper, the implementations of a $0.1{\mu}m$ gallium arsenide (GaAs) pseudomorphic high electron mobility transistor process for a low noise amplifier (LNA), a subharmonically pumped (SHP) mixer, and a single-chip receiver for 70/80 GHz point-to-point communications are presented. To obtain high-gain performance and good flatness for a 15 GHz (71 GHz to 86 GHz) wideband LNA, a five-stage input/output port transmission line matching method is used. To decrease the package loss and cost, 2nd and 4th SHP mixers were designed. From the measured results, the five-stage LNA shows a gain of 23 dB and a noise figure of 4.5 dB. The 2nd and 4th SHP mixers show conversion losses of 12 dB and 17 dB and input P1dB of -1.5 dBm to 1.5 dBm. Finally, a single-chip receiver based on the 4th SHP mixer shows a gain of 6 dB, a noise figure of 6 dB, and an input P1dB of -21 dBm.

Design of the Low Noise Amplifier and Mixer Using Newly Bias Circuit for S-band (새로운 바이어스 회로를 적용한 S-band용 저잡음 증폭기 및 믹서의 One-Chip 설계)

  • Kim Yang-Joo;Shin Sang-Moon;Choi Jae-Ha
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.16 no.11 s.102
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    • pp.1114-1122
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    • 2005
  • In this paper, the study of a design, fabrication and measurement of the receiver MMIC LNA, mixer for S-band application is described. The LNA is designed by 2-stage common source. The mixer is composed of active LO and RF balun to integrate on a chip and applied a newly proposed bias circuit to compensate the process variations of active devices. The LNA has 15.51 dB-gain and 1.02dB-Noise Figure at 2.1 GHz. The conversion gain of the mixer is -12 dB, IIP3 is approximately 4.25 dBm and port-to-port isolation is over 25 dB. The newly proposed bias circuit is composed of a few FETs and resistors, and can compensate the variation of the threshold voltage by the process variations, temperature changes and etc. The designed chip size is $1.2[mm]\times1.4[mm]$.

System Level Design of Multi-standard Receiver Using Reconfigurable RF Block

  • Kim, Chang-Jae;Jang, Young-Kyun;Yoo, Hyung-Joun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.4 no.3
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    • pp.174-181
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    • 2004
  • In this paper, we review the four receiver architectures and four methods for multi-standard receiver design. Propose reconfigurable RF block can be used for both low-IF and direct conversion architecture. Also, using reconfigurable mixer method, it can be operated at $2{\sim}6$ GHz range for multi-standard receiver. It consists of wideband mixer, filter, and automatic gain control amplifier and to get wide-band operation, $2{\sim}6$ GHz, wide-band mixer use flexible input matching method. Besides, to design multi-standard receiver, LNA bank that support each standard is necessary and it has good performance to compensate the performance of wide-band mixer. Finally, we design and simulate proposed reconfigurable RF block and to prove that it has acceptable performances for various wireless standards, the LNA bank that supports both IEEE 802.11a/b/g and WCDMA is also designed and simulated with it.

A 0.13 ㎛ CMOS Dual Mode RF Front-end for Active and Passive Antenna (능·수동 듀얼(Dual) 모드 GPS 안테나를 위한 0.13㎛ CMOS 고주파 프론트-엔드(RF Front-end))

  • Jung, Cheun-Sik;Lee, Seung-Min;Kim, Young-Jin
    • Journal of Advanced Navigation Technology
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    • v.13 no.1
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    • pp.48-53
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    • 2009
  • The CMOS RF front-end for Global Positioning System(GPS)are implemented in 1P8M CMOS $0.13{\mu}m$ process. The LNAs consist of LNA1 with high gain and low NF, and LNA2 with low gain and high IIP3 for supporting operation with active and passive antenna. the measured performances of both LNAs are 16.4/13.8 dB gain, 1.4/1.68 dB NF, and -8/-4.4 dBm IIP3 with 3.2/2 mA form 1.2 V supply, respectively. The quadrature downconversion mixer is followed by transimpedance amplifier with gain controllability from 27.5 to 41 dB. The front-end performances in LNA1 mode are 39.8 dB conversion gain, 2.2 dB NF, and -33.4 dBm IIP3 with 6.6 mW power consumption.

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5.25GHz Image Rejection Low Noise Amplifier and Mixer for Wireless LAN (무선랜을 위한 5.25GHz 이미지 제거 저 잡음 증폭기 및 믹서 설계)

  • Lee, Jun-Jae;Kong, Dong-Ho;Choo, Sung-Joong;Park, Jung-Ho
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.893-896
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    • 2005
  • This paper describes Low Noise Amplifier(LNA) and Single Balanced Mixer(SBM) with monolithic image rejection notch filter using 0.5um MESFET process. LNA, Notch filter, and SBM were integrated on a chip. This chip does not need off chip SAW filter, thereby reducing the overall cost and system volume. The LNA with Notch filter provides a gain of 15dB, noise figure of 1.2dB, and image rejection ratio of -74dB. The SBM has a conversion gain of 6dB.

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Wideband VHF and UHF RF Front-End Receiver for DVB-H Application

  • Park, Joon-Hong;Kim, Sun-Youl;Ho, Min-Hye;Baek, Dong-Hyun
    • Journal of Electrical Engineering and Technology
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    • v.7 no.1
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    • pp.81-85
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    • 2012
  • This paper presents a wideband and low-noise direct conversion front-end receiver supporting VHF and UHFbands simultaneously. The receiver iscomposed of a low-noise amplifier (LNA), a down conversion quadrature mixer, and a frequency divider by 2. The cascode configuration with the resistor feedback is exploited in the LNA to achieve a wide operating bandwidth. Four gainstep modesare employed using a switched resistor bank and a capacitor bank in the signal path to cope with wide dynamic input power range. The verticalbipolar junction transistors are used as the switching elements in the mixer to reduce 1/f noise corner frequency. The proposed front-end receiver fabricated in 0.18 ${\mu}m$ CMOS technology shows very low minimum noise figureof 1.8 dB and third order input intercept pointof -12dBm inthe high-gain mode of 26.5 dBmeasured at 500 MHz.The proposed receiverconsumeslow current of 20 mA from a 1.8 V power supply.

Design of a RF Front-End for 2.45GHz Band using Sub-harmonic Active Mixer (Sub-harmonic 능동형 혼합기를 이용한 2.45GHz 직접변환 수신기용 RF Front-End 설계 방법에 관한 연구)

  • Lim, Tae-Seo;Ko, Jae-Hyeong;Jung, Hyo-Bin;Kim, Hyeong-Seok
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.57 no.7
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    • pp.1235-1240
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    • 2008
  • In this paper, we presented an active RFID system in 2.45GHz range including LNA, Mixer and gain block. And in this work, a link budget model for RFID applications are proposed. We describe the detailed design and implementation of our system. Our components in RFID system has features such as low Noise Figure, reliable energy budget, and standard compliance with ISO 18000-4. Our receiver is effective for development and evaluation of prototype applications because of the flexibility of the design hardware. So, our platform will be suitable for versatile item management applications.