• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1355-1362
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.11
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• pp.972-978
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• 2012

LDPC (low density parity check) code shows near Shannon limit performance by iterative decoding based on sum-product algorithm (SPA). Message updating procedure between variable and check nodes in SPA is done by a scheduling method. LDPC code shows different performance according to scheduling schemes. The conventional researches have been shown that the shuffled BP (belief propagation) algorithm shows better performance than the standard BP algorithm although it needs less number of iterations. However the reason is not analyzed clearly. Therefore the reason of difference in performance according to LDPC decoding algorithms is analyzed in this paper. 4 cases according to satisfaction of parity check condition are considered and compared. As results, the difference in the updating procedure in a cycle in the parity check matrix is considered to be the main reason of performance difference.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.5 s.311
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• pp.68-75
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• 2006

Multimedia fingerprinting protects multimedia content from illegal redistribution by uniquely marking every copy of the content distributed to each user. Differ from a symmetric/asymmetric scheme, fingerprinting schemes, only regular user can know the inserted fingerprint data and the scheme guarantee an anonymous before recontributed data. In this paper, we present a scheme which is the algorithm using LDPC(Low Density Parity Check) for detection of colluded multimedia fingerprint and correcting errors. This proposed scheme is consists of the LDPC block, Hopfield Network and the algorithm of anti-collusion code generation. Anti-collusion code based on BIBD(Balanced Incomplete Block Design) was made 100% collusion code detection rate about the linear collusion attack(average, AND and OR) and LD% block for the error bits correction confirmed that can correct error until AWGN 0dB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11C
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• pp.901-906
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• 2010

Low density parity check (LDPC) code, first introduced by Gallager and re-discovered by MacKay et al, has attracted researcher's interest mainly due to their performance and low decoding complexity. It was remarkable that the performance is very close to Shannon capacity limit under the assumption of having long codeword length and iterative decoder. However, comparing to turbo codes widely used in the current mobile communication, the encoding complexity of LDPC codes has been regarded as the drawback. This paper proposes a solution for DVB-S2 LDPC encoder to reduce the encoder latency. We use the fast IRA encoder that use the transformation of the parity check matrix into block-wise form and the partial parallel process to reduce the number of system clocks for the IRA code encoding. We compare the proposed encoder with the current DVB-S2 encoder to show that the performance of proposal is better than that of the current DVB-S2 encoder.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2465-2473
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• 2011

This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems including WiMAX and WLAN. A new design of DFU based on sign-magnitude arithmetic instead of two's complement arithmetic is proposed, resulting in 18% reduction of gate count for 96 DFUs array used in mobile WiMAX LDPC decoder. A multi-mode LDPC decoder for mobile WiMAX standard is designed using the proposed DFU. The LDPC decoder synthesized using a 0.18-${\mu}m$ CMOS cell library with 50 MHz clock has 268,870 gates and 71,424 bits RAM, and it is verified by FPGA implementation.

• Journal of Korea Society of Industrial Information Systems
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• v.22 no.3
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• pp.19-26
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• 2017

In this paper, a Linear Error Correction Code, Which is Applicable to Next Generation Wireless Communication System Technology, is Constructed Based on Performance Comparison and Transmission Based on the Premise of High Performance Mobile Rate Enhancement System. This is Because Data Rates are Becoming an Important Issue in Reed-Solomon Codes and Linear Error Code (LDPC) Used in the Physical Layer of Digital Communication and Broadcasting Technologies. Therefore, this paper Simulates the Performance of Reed - Solomon Code and LDPC Applied to Mobile Broadcasting DVB (Digital Video Broadcasting) System and Mobile Broadcasting in Digital Communication and Broadcasting, At this time, Technical Aspects of the Transmission Efficiency and Performance of the LDPC Replacing the Existing Reed-Solomon Code have been Verified from the Viewpoint of Efficiency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.8
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• pp.637-642
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• 2014

In this paper, we propose a efficient shift index searching algorithm for design of the block LDPC codes. It is combined with the message-passing based cycle search algorithm and ACE algorithm. We can determine the shift indices by ordering of priority factors which are effect on the LDPC code performance. Using this algorithm, we can construct the LDPC codes with low complexity compare to trellis-based search algorithm and save the memory for storing the parity check matrix.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.1
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• pp.117-124
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• 2012

In this paper, we propose a simple H parity check matrix from the CPM(circulant permutation matrix), which can easily avoid the cycle-4, and approach to flexible code rates and lengths. As a result, the operations of the submatrices will become the multiplications between several CPMs, the calculations of the LDPC(low density parity check) encoding could be simplest. Also we consider the fast encoding problem for LDPC codes. The proposed constructions could lead to fast encoding based on the simplest matrices operations for both regular and irregular LDPC codes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.11
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• pp.2295-2303
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• 2009

Underwater acoustic(UWA) communication has multipath error because of reflection by sea-level and sea-bottom. The multipath of UWA channel causes signal distortion and error floor. In this paper, we proposed the compensation method of multipath effect using the impulse response of the UWA channel and then analysis the performance of channel coding such as LDPC code, concatenate code. Also we analysed the time-delay errors and estimated amplitude errors of estimated channel information and its affection on the performance. As shown in simulation results, the performance of proposed compensation method is better than the performance of conventional method.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.1
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• pp.38-46
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• 2012

In this paper, we propose a decision feedback equalizer based on LDPC(Low Density Parity Check) code for the fast processing and performance improvement in OFDM system. LDPC code has good error correcting capability and its performance approaches the Shannon capacity limit. However, it has longer parity check matrix and needs more iteration numbers. In our proposed system, MSE(Mean Square Error) of signal between decision device and decoder is fed back to equalizer. This proposed system can improve BER performance because it corrects estimated channel response more accurately. In addition, the proposed system can reduce complexity because it has a lower number of iterations than system without feedback at the same performance. Simulation results evaluate and show the performance of OFDM system with the CFO and phase noise in multipath channel.