• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.22-30
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• 2011

In this paper, we propose a memory efficient multi-rate Low Density Parity Check (LDPC) decoder for China Mobile Multimedia Broadcasting (CMMB). We find the best trade-off between the performance and the circuit area by designing a partially parallel decoder which is capable of passing multiple messages in parallel. By designing an efficient address generation unit (AGU) with an index matrix, we could reduce both the amount of memory requirement and the complexity of computation. The proposed regular LDPC decoder was designed in Verilog HDL and was synthesized by Synopsys' Design Compiler using Chartered $0.18{\mu}m$ CMOS cell library. The synthesized design has the gate size of 455K (in NAND2). For the two code rates supported by CMMB, the rate-1/2 decoder has a throughput of 14.32 Mbps, and the rate-3/4 decoder has a throughput of 26.97 Mbps. Compared with a conventional LDPC for CMMB, our proposed design requires only 0.39% of the memory.

• Journal of Broadcast Engineering
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• v.15 no.5
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• pp.681-696
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• 2010

In this paper, we examined the possibility of the transmission capacity increase by an extension and a modification of ATSC 8-VSB transmission system[1] for broadcasting a 3D HDTV services through 6 MHz terrestrial channel. First we examined the performance and the limit of conventional ATSC 8-VSB transmission system. After that LDPC & BCH code are employed instead of conventional RS & TCM code and the transmission parameter is founded for the capacity increase with resonable TOV by varying the code-rates and increasing the modulation constellation. We do not consider the perfect backward compatibility for maximum transmission capacity increase like DVB-S2 system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2783-2790
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• 2010

In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen 802.11n for wireless local access network(WLAN) standard, require a large number of computation due to large size of coded block and iteration. Therefore, we presented three kinds of low computational algorithms for LDPC codes. First, sequential decoding with partial group is proposed. It has the same H/W complexity, and fewer number of iterations are required with the same performance in comparison with conventional decoder algorithm. Secondly, we have apply early stop algorithm. This method reduces number of unnecessary iterations. Third, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and early stop algorithm is reduced more than one iteration and computational complexity of early detected method is about 30% offs in case of check node update, 94% offs in case of check node update compared to conventional scheme. The LDPC decoder have been implemented in Xilinx System Generator and targeted to a Xilinx Virtx5-xc5vlx155t FPGA. When three algorithms are used, amount of device is about 45% off and the decoding speed is about two times faster than convectional scheme.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.7
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• pp.3156-3167
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• 2020

One drawback of polar codes is that they are not universal, that is, to achieve optimal performance, different polar codes are required for different kinds of channel. This paper proposes a polar code construction scheme for Nakagami-m fading channel. The scheme fully considers the characteristics of Nakagami-m fading channel, and uses the optimized Bhattacharyya parameter bounds. The constructed code is applied to an orthogonal frequency division multiplexing (OFDM) system over Nakagami-m fading channel to prove the performance of polar code. Simulation result shows the proposed codes can get excellent bit error rate (BER) performance with successive cancellation list (SCL) decoding. For example, the designed polar code with cyclic redundancy check (CRC) aided SCL (L = 8) decoding achieves 1.1dB of gain over LDPC at average BER about 10^-5 under 4-quadrature amplitude modulation (4QAM) while the code length is 1024, rate is 0.5.

• Journal of Broadcast Engineering
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• v.15 no.6
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• pp.749-756
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• 2010

The signal space diversity is one of the promising transmission techniques in next generation mobile TV service. However, DVB-T2 does not consider the multiple antennas (MIMO) so that the cyclic Q-delay method, a component interleaver in DVB-T2, causes a critical issue in detecting symbols at the receiver side by increasing the inter-symbol dependency. To solve this problem, the component-swapping technique is proposed, which limits the inter-symbol dependency in order to reduce detection complexity. In this paper, the achievable gain of a component-swapping technique combined with 16K LDPC code defined in DVB-T2 is evaluated by computer simulations. From the results, the gain is confirmed in terms of BER and receive complexity compared to legacy component interleaver methods.

• Journal of Satellite, Information and Communications
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• v.8 no.4
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• pp.21-25
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• 2013

The dual-stream based stereoscopic 3D HDTV broadcasting service was launched recently. Although the dual-stream based HDTV service has been successfully provided, the 3D HDTV broadcasting system requires more bandwidth efficient transmission schemes because it should convey both left and right HD resolution images simultaneously in the finite 6MHz bandwidth. In this paper, we consider more advanced ATSC transmission schemes that use higher modulation such as 16-QAM and concatenated RS code and block LDPC codes. Compared with conventional ATSC system and the modified ATSC system in [2], the proposed system has about 2.97dB and 1.12dB SNR gain at the payload data rate of 19.44Mbps compared with the existing ATSC system and the modified ATSC system [2]. Also, the proposed scheme requires only 1.05dB power increase for the 3D HDTV service, which is reasonable SNR increase value and applicable to the advanced 3D high definition broadcasting realization in limited 6MHz bandwidth.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2143-2149
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• 2012

DVB-S2 employs LDPC codes which approach to the Shannon's limit, since it has characteristics of a good distance, error floor does not appear. Furthermore it is possible to processes full parallel processing. However, it is very difficult to high speed decoding because of a large block size and number of many iterations. This paper present HSS algorithm to reduce the iteration numbers without performance degradation. In the flooding scheme, the decoder waits until all the check-to-variable messages are updated at all parity check nodes before computing the variable metric and updating the variable-to-check messages. The HSS algorithm is to update the variable metric on a check by check basis in the same way as one code draws benefit from the other. Eventually, LDPC decoding speed based on HSS algorithm improved 30% ~50% compared to conventional one without performance degradation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.12C
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• pp.1135-1141
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• 2007

In this paper, an adaptive bit-reliability mapping is proposed for the bit-level Chase combining in LDPC-coded high-order modulation systems. Contrary to the previously known bit-reliability mapping that assigns the information (or parity) bits to more (or less) reliable bit positions, the proposed mapping adaptively assigns codeword bits to the bit positions of various reliabilities by considering the characteristics of code and protection levels of bits in high-order modulation symbol. Compared with the symbol-level Chase combining and the constellation rearrangement bit mapping, the proposed mapping gives $0.7{\sim}1.3$ dB and $0.1{\sim}1.0$ dB performance gain at $FER=10^{-3}$ with no additional complexity, respectively. Adaptive bit-reliability mappings are derived for various environments and the validity of them is confirmed through simulation.

• ETRI Journal
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• v.31 no.2
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• pp.240-242
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• 2009

A computationally efficient implementation of the progressive edge-growth algorithm is presented. This implementation uses an array of red-black (RB) trees to manage the layered structure of check nodes and adopts a new strategy to expand the Tanner graph. The complexity analysis and the simulation results show that the proposed approach reduces the computational effort effectively. In constructing a low-density parity check code with a length of $10^4$, the RB-tree-array-based implementation takes no more 10% of the time required by the original method.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.07a
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• pp.387-387
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• 2004