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A Memory-efficient Partially Parallel LDPC Decoder for CMMB Standard  

Park, Joo-Yul (Department of Electronics Computer Engineering, Hanyang University)
Lee, So-Jin (Hyundai Motors)
Chung, Ki-Seok (Department of Electronic Engineering, Hanyang University)
Cho, Seong-Min (Department of Electronics Computer Engineering, Hanyang University)
Ha, Jin-Seok (Department of Electronics Computer Engineering, Hanyang University)
Song, Yong-Ho (Department of Electronic Engineering, Hanyang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.48, no.1, 2011 , pp. 22-30 More about this Journal
Abstract
In this paper, we propose a memory efficient multi-rate Low Density Parity Check (LDPC) decoder for China Mobile Multimedia Broadcasting (CMMB). We find the best trade-off between the performance and the circuit area by designing a partially parallel decoder which is capable of passing multiple messages in parallel. By designing an efficient address generation unit (AGU) with an index matrix, we could reduce both the amount of memory requirement and the complexity of computation. The proposed regular LDPC decoder was designed in Verilog HDL and was synthesized by Synopsys' Design Compiler using Chartered $0.18{\mu}m$ CMOS cell library. The synthesized design has the gate size of 455K (in NAND2). For the two code rates supported by CMMB, the rate-1/2 decoder has a throughput of 14.32 Mbps, and the rate-3/4 decoder has a throughput of 26.97 Mbps. Compared with a conventional LDPC for CMMB, our proposed design requires only 0.39% of the memory.
Keywords
CMMB; Low Density Parity Check(LDPC) codes; Multi-rate support; Partially parallel decoder;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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1 J. G. Park and C. H. Lee, "Architecture of an LDPC Decoder for DVB-S2 using reuse Technique of processing units and Memory relocation", Journal of the Institute of Electronics Engineers of Korea, Vol.43 SD, No.9, Sept 2006, pp. 31-37.
2 L. Yang, M. Shen, H. Liu and C. J. R. Shi, "An FPGA Implementation of Low-Density Parity-Check Code Decoder with Multi-Rate Capability", ASP-DAC, Volume 2, Jan 2005, pp. 760-763.
3 Z. Wang, "Low-complexity high-speed decoder design for quasi-cyclic LDPC codes," IEE Trans. VLSI systems, vol.15, no.1, 2007.
4 Interfax China (2006-10-25). China releases mobile TV industrial standard. Retrieved on 2007-04-14
5 Mobile Multimedia Broadcasting (P. R. China) Part 1: Framing Structure, Channel Coding and Modulation for Broadcasting Channel
6 F. Kienle, T. Brack, and N. Wehn, "A synthesizable IP core for DVB-S2 LDPC code decoding," in Proc. DATE, Munich, Germany, Vol.3, Mar. 2005, pp. 100-105.
7 Wang Peng, Chen Youg-en, "Low-complexity Real-time LDPC Encoder Design for CMMB", International Conference on Intelligent Information Hiding and Multimedia Signal Processing, Aug. 2008, pp. 1209-1212.
8 R. G. Gallager, "Low density parity check codes", IRE Trans. Inform. Theory, Vol. IT-8, Jan 1962, pp. 21-28.
9 D. J. C. Mackay and R. M. Neal, "Neal Shannon Limit Performance of Low Density Parity check codes", Electron. Lett, Vol. 32, Aug 1996, pp. 1645-1646.   DOI   ScienceOn