• 전자공학회논문지 IE
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• v.43 no.4
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• pp.115-121
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• 2006

In this paper, we proposed about data error check and correction on channel transmission in the communication system. LDPC codes are used for minimizing channel errors by modeling AWGN Channel as a VDSL system. Because LDPC Codes use low density parity bit, mathematical complexity is low and relating processing time becomes shorten. Also the performance of LDPC code is better than that of turbo code in long code word on iterative decoding algorithm. This algorithm is better than conventional algorithms to correct errors, the proposed algorithm assigns weights for errors concerning parity bits. The proposed weighted Bit-flipping algorithm is better than the conventional Bit-flipping algorithm and we are recognized improve gain rate of 1 dB.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.4
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• pp.569-574
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• 2017

In order to transmit information in a channel environment in which noise exists, a coding technique of information is required. One of the coding techniques used for error detection and correction close to the Shannon limit is Low Density Parity Code(LDPC). LDPC and decoding characteristic features by Sum-product algorithm are matched for the performance to Turbo Code, RA(Repeat Accumulate) code, in case of very long code length of LDPC surpass their performance. This paper explains LDPC coding scheme of image data and decoding scheme, implements LDPC decoder in FPGA.

• ETRI Journal
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• v.39 no.3
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• pp.319-325
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• 2017

The decoding process of a quasi-cyclic low-density parity check code requires a unique type of rotator. These rotators, called multi-size cyclic-shifters (MSCSs), rotate input data with various sizes, where the size is the amount of data to be rotated. This paper proposes a low-complexity MSCS structure for the case when the sizes have a nontrivial common divisor. By combining the strong points of two previous structures, the proposed structure achieves the smallest area. The experimental results show that the area reduction was more than 14.7% when the proposed structure was applied to IEEE 802.16e as an example.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2006.11a
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• pp.229-232
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• 2006

본 논문은 AWGN 채널상의 Single Parity Check(SPC) 다차원 product부호에서 LDPC(Low Density Parity Check)부호를 이용한 오류 정정의 성능을 제시한다. 기존 방법인 터보 부호 방식을 이용한 오류 정정과 비교하여 LDPC부호가 갖는 장점을 기술하고 실험을 통해 LDPC 부호를 이용한 오류 정정 성능도 터보부호와 대등함을 보인다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2367-2372
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• 2015

One of various low-density parity-check(LDPC) codes that has been adopted in many communication standards due to its error correction ability is a quasi-cyclic LDPC(QC-LDPC) code, which leads to comparable decoder complexity. One of the main blocks in the QC-LCDC code decoder is a multi-size circular shifter(MSCS) that can perform various size rotation. The MSCS can be implemented with many structures, one of which is based on Banes network. The Benes network structure can perform the normal MSCS operation efficiently, but it cannot use the properties coming from specifications like rotation sizes. This paper proposesd a scheme where the Benes network structure can use the rotation size property with the modification of the control signal generation. The proposed scheme is applied to the MSCS of IEEE 802.16e WiMAX QC-LDPC decoder to reduce the number of MUXes and the critical path delay.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.2
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• pp.196-201
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• 2013

In this paper, we proposed high speed LDPC encoder architecture for DVB-S2 standard. In conventional algorithm, the processes of parity calculations are serial fashion. Therefore conventional algorithm need clocks of number of parity. The proposed LDPC encoding architecture is based on a parallel 360 bits-wise operations. The key issues for realizing high speed are using the two kinds of index addresses and make use of memories efficiently. We implemented a half rate LDPC encoder on an FPGA, and confirmed its maximum throughput is up to 10 Gbps on 100MHz clock.

• Journal of Korea Multimedia Society
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• v.9 no.6
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• pp.728-734
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• 2006

Carrier interferometry code is considered as a promising scheme that provides significant performance improvement via frequency diversity effect. Space-time coding is commonly employed to achieve a performance gain through space diversity. The combination of these techniques and forward error correction coding will lead to enhanced system capacity and performance. This paper presents a low-density parity check (LDPC) coded space-time orthogonal frequency division multiplexing (OFDM) transmission scheme with carrier interferometry code for high-capacity and high-performance mobile multimedia communications. Computer simulations demonstrate that the proposed mobile multimedia transmission system offers a considerable performance improvement of approximately 9dB in terms of Eb/No in the Rayleigh fading channel with relatively low delay spread, in comparison with space-time OFDM. Performance gains are further increased, comparing with traditional OFDM systems.

• Journal of Communications and Networks
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• v.17 no.3
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• pp.213-220
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• 2015

In this paper, we present a reliability-based iterative proportionality-logic decoding algorithm for two classes of structured low-density parity-check (LDPC) codes. The main contributions of this paper include: 1) Syndrome messages instead of extrinsic messages are processed and exchanged between variable nodes and check nodes, which can reduce the decoding complexity; 2) a more flexible decision mechanism is developed in which the decision threshold can be self-adjusted during the iterative process. Such decision mechanism is particularly effective for decoding the majority-logic decodable codes; 3) only part of the variable nodes satisfying the pre-designed criterion are involved for the presented algorithm, which is in the proportionality-logic sense and can further reduce the computational complexity. Simulation results show that, when combined with factor correction techniques and appropriate proportionality parameter, the presented algorithm performs well and can achieve fast decoding convergence rate while maintaining relative low decoding complexity, especially for small quantized levels (3-4 bits). The presented algorithm provides a candidate for those application scenarios where the memory load and the energy consumption are extremely constrained.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.11
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• pp.2637-2642
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• 2015

The low-density parity check(LDPC) code is being widely used due to its outperformed error-correction ability. The decoder of the quasi-cyclic LDPC(QC-LDPC) codes, a kind of LDPC codes, requires a multi-size cyclic shifter(MSCS) performing rotation of various sizes. The MSCS can be implemented with a Benes network, which requires a $3{\times}3$ switch if the number of data to be rotated is a multiple of 3. This paper proposes a control signal generation with lower complexity and a faster $3{\times}3$ switch. For the experiment, the proposed schemes are applied to the MSCS of an IEEE 802.16e WiMAX QC-LDPC code decoder. The result shows that the delay is reduced by about 8.7%.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.891-892
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• 2008

본 논문에서는 최근 주목받고 있는 에러 정정 기법 중 하나인 LDPC(Low Density Parity Check) 부호를 광 기록 채널(Optical Recording Channel)에 적용해 보았고 이때 사용되는 연판정 출력 알고리즘으로 MAP과 SOVA를 이용하여 성능을 비교하였다.