• Title/Summary/Keyword: LDD 임플란트

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A study on the Hot Carrier Injection Improvement of I/O Transistor (I/O 트랜지스터의 핫 캐리어 주입 개선에 관한 연구)

  • Mun, Seong-Yeol;Kang, Seong-Jun;Joung, Yang-Hee
    • The Journal of the Korea institute of electronic communication sciences
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    • v.9 no.8
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    • pp.847-852
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    • 2014
  • As the scaling trend becomes accelerated in process technology for cost reduction in semiconductor chip manufacturing, the requirement for shrink technology has increased. Hot Carrier Injection (HCI) degradation for I/O transistors is most concerning part when shrink. To solve this, the effective channel length (Leff) was increased using liner oxide before Light Doped Drain (LDD) implants and optimized the tilt angle to increase Leff without E-field degradation in LDD region, satisfying the HCI specification.

A Study on the DC parameter matching according to the shrink of 0.13㎛ technology (0.13㎛ 기술의 shrink에 따른 DC Parameter 매칭에 관한 연구)

  • Mun, Seong-Yeol;Kang, Seong-Jun;Joung, Yang-Hee
    • The Journal of the Korea institute of electronic communication sciences
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    • v.9 no.11
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    • pp.1227-1232
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    • 2014
  • This paper relates 10% shrink from $0.13{\mu}m$ design for core devices as well as input and output (I/O) devices different from previous poly length shrink size only. We analyzed body effect with different channel length and doping profile simulation. After fixing the gate oxide module process, LDD implant conditions were optimized such as decoupled plasma nitridation of gate oxide, TEOS oxide $100{\AA}$ before LDD implant and 22o tilt-angle(45o twist-angle) LDD implant respectively to match the spice DC parameters of pre-shrink and finally matched them within 5%.

Analysis of a Novel Elevated Source Drain MOSFET with Reduced Gate-Induced Drain Leakage and High Driving Capability (Gate-Induced Drain Leakage를 줄인 새로운 구조의 고성능 Elevated Source Drain MOSFET에 관한 분석)

  • Kim, Gyeong-Hwan;Choe, Chang-Sun;Kim, Jeong-Tae;Choe, U-Yeong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.6
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    • pp.390-397
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    • 2001
  • A novel self-aligned ESD (Elevated Source Drain) MOSFET structure which can effectively reduce the GIDL (Gate-Induced Drain Leakage) current is proposed and analyzed. The proposed ESD structure is characterized by sidewall spacer and recessed-channel depth which are determined by dry-etching process. Elevation of the Source/Drain extension region is realized so that the low-activation effect caused by low-energy ion implantation can be avoided. Unlike the conventional LDD structures, it is shown that the GIDL current of the ESD structure is suppressed without sacrificing the maximum driving capability. The main reason for the reduction of GIDL current Is the decreased electric field at the point of the maximum band-to-band tunneling as the peak electric field is shifted toward the drain side.

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