• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 I
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• pp.270-273
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• 2003

The design, fabrication, and measured result of a 4.7 GHz differential VCO (Voltage Controlled Oscillator) for a 5.2 GHz WLAN (Wireless Local Area Network) applications is presented. The circuit is designed in a 0.35 mm technology employing three metal layers. The design is based on a fully integrated LC tank using spiral inductors. Measured tuning range is 10% of oscillation frequency with a control voltage from 0 to 3.0 V. Oscillation power of $\square$ 2.3 dBm at 4.63 GHz is measured with 21 mA DC current at 3V supply. The phase noise is $\square$ 104.17 dBc/Hz at 1 MHz offset.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권3호
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• pp.153-159
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• 2009

A CMOS frequency synthesizer for $5{\sim}6$ GHz UNII-band sub-harmonic direct-conversion receiver has been developed. For quadrature down-conversion with sub-harmonic mixing, octa-phase local oscillator (LO) signals are generated by an integer-N type phase-locked loop (PLL) frequency synthesizer. The complex timing issue of feedback divider of the PLL with large division ratio is solved by using multimodulus prescaler. Phase noise of the local oscillator signal is improved by employing the ring-type LC-tank oscillator and switching its tail current source. Implemented in a $0.18{\mu}m$ CMOS technology, the phase noise of the LO signal is lower than -80 dBc/Hz and -113 dBc/Hz at 100 kHz and 1MHz offset, respect-tively. The measured reference spur is lower than -70 dBc and the power consumption is 40 m W from a 1.8 V supply voltage.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.155-158
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• 2004

This paper proposes a soft-transition control strategy for a three phase ZCS(Zero Current Switching) inverter circuit. Each phase leg of inverter circuit consists of an LC resonant tank, two main switches, and two auxiliary switches. This paper presents design consideration via a study example of a three phase prototype inverter for motor drives. A simple device tester with zero current switching capability is proposed to select eligible auxiliary switches. The principle of operation, feature and design consideration is illustrated and verified through the experiment with a 2.2kW 5kHz IGBT based experimental circuit.

• 한국정보통신학회논문지
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• 제9권2호
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• pp.301-306
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• 2005

본 논문에서는 gain-boosting 회로를 이용하여 전류 미스매치를 줄일 수 있는 전하펌프와 전압제어 저항기를 사용하여 선형성이 우수한 래치 구조의 전압제어발생기를 제안하여 위상고정루프를 설계하였다. Cain-boosting 전하펌프를 사용한 위상고정루프는 루프필터 출력 전압 구간에서 11$mu$V(최대 43$mu$V, 최소 32$mu$V)의 전압 흔들림 차이를 나타내었다. 전압제어저항기를 이용한 전압제어발진기는 입력전압 동작 구간에서 우수한 선형성을 나타내었다. 또한 제작된 전압제어발진기의 위상 잡음 특성은 -1084Bc/Hz(a)100kHz이며 CMOS 공정으로 만들어진 LC 전압제어발진기와 비슷한 성능을 가진다. 0.35$mu$m CMOS 공정으로 시뮬레이션 하였으며 록킹 시간은 150$mu$s이다.

• 한국통신학회논문지
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• 제24권8A호
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• pp.1252-1258
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• 1999

본 논문에서는 10-MHz 대역폭을 갖는 무선가입자망용 중간주파수 아날로그 IC 설계에 관하여 논한다. 본 IC는 RF 부와 MODEM사이에서 인터페이스 역할을 하며, 수신 단에서는 중간주파수 신호를 기저대역으로 저역변환을 하고 송신 단에서는 기저대역 신호를 중간주파수 신호로 바꾸어 준다. 본 회로는 이득조절증폭기, 위상잠금회로, 저역통과필터, 아날로그-디지털 및 디지털-아날로그 변환기로 구성된다. 위상잠금회로에서 전압발진기 및 분주기, 위상비교기, 전하펌핑회로는 동일 칩 안에 구현하였고, 외부소자로는 루프필터용 소자와 LC 탱크 소자만이 사용되었다. 본 IC는 0.6-$\mu\textrm{m}$ CMOS 공정에 의하여 제작되었고, 전체 크기는 4 mm $\times$ 4 mm 이며, 3.3 V에서 약 57mA를 소모하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권4호
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• pp.192-197
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• 2009

This paper presents the design and measurement of a 2.4/5.2-GHz dual band VCO with a balanced frequency doubler in $0.18\;{\mu}m$ CMOS process. The topology of a 2.4 GHz VCO is a cross-coupled VCO with a LC tank and the frequency of the VCO is doubled by a frequency balanced doubler for a 5.2 GHz VCO. The gate bias matching network for class B operation in the balanced doubler is adopted to obtain as much power at 2nd harmonic output as possible. The average output powers of the 2.4 GHz and 5.2 GHz VCOs are -12 dBm and -13 dBm, respectively, the doubled VCO has fundamental harmonic suppression of -25 dB. The measured phase noises at 5 MHz frequency offset are -123 dBc /Hz from 2.6 GHz and -118 dBc /Hz from 5.1 GHz. The total size of the dual band VCO is $1.0\;mm{\times}0.9\;mm$ including pads.

• Journal of Electrical Engineering and Technology
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• 제13권6호
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• pp.2441-2446
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• 2018

This paper presents a radio frequency-to-direct current (RF-to-DC) converter for special RF power harvesting application at 915 MHz. The major featured components of the proposed RF-to-DC converter is the combination of a cross-coupled rectifier and an active diode: first, the cross-coupled rectifier boosts the input voltage to desired level, and an active diode blocks the reverse current, respectively. A prototype was implemented using $0.18{\mu}m$ CMOS technology, and the performance was proven from the fact that the targeted RF harvesting system's full-operation with higher power efficiency; even if the system's input power gets lower (e.g., from nominal 0 to min. -12 dBm), the proposed RF-to-DC converter constantly provides 1.47 V, which is exactly the voltage level to drive follow up system components like DC-to-DC converter and so on. And, maximum power conversion efficiency is 82 % calculated from the 0 dBm input power, 2.3 mA load current.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권5호
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• pp.437-444
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• 2015

In simulation-based circuit optimization, many simulation runs may be wasted while evaluating infeasible designs, i.e. the designs that do not meet the constraints. To avoid such a waste, this paper investigates the use of support vector machine (SVM) classifiers in predicting the design's feasibility prior to simulation and the optimal selection of the SVM parameters, namely, the Gaussian kernel shape parameter ${\gamma}$ and the misclassification penalty parameter C. These parameters affect the complexity as well as the accuracy of the model that SVM represents. For instance, the higher ${\gamma}$ is good for detailed modeling and the higher C is good for rejecting noise in the training set. However, our empirical study shows that a low ${\gamma}$ value is preferable due to the high spatial correlation among the circuit design candidates while C has negligible impacts due to the smooth and clean constraint boundaries of most circuit designs. The experimental results with an LC-tank oscillator example show that an optimal selection of these parameters can improve the prediction accuracy from 80 to 98% and model complexity by $10{\times}$.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2000년도 종합학술발표회 논문집 Vol.10 No.1
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• pp.150-153
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• 2000

In this paper, we have designed a 2 stage MMIC power amplifier which has flat gains of in-band and reasonable out-band cutoff characteristics using 0.5$\mu\textrm{m}$ MESFET libra교 of ETRI. For the 1st stave, we obtaind P$_{1dB}$ of 9.2 dBm and gain 10.8 dB using 6 finger D-MESFET and P$_{1dB}$ of 18.4 dBm and gain of 10.8 dB using 14 finger D-MESFET for the 2nd stage, which is power matched using LIBRA's embedded TUNER. Also in-band gain flatness and out-band cutoff characteristics are obtained by attaching LC tank in the output matching circuit. The designed 2 stage MMIC power amplifier has bandwidth of 0.95～2.8 GHz, gain of 20 dB and P$_{1dB}$of 17.2 dBm. Especially gain flatness of $\pm$0.8dB was obtained in 1.8～2.5 GHz frequency ranges. And chip size is 1.4$\times$1.4 mm..4 mm.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.443-450
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• 2016

The linearization technique for low noise amplifier (LNA) has been implemented in standard $0.18-{\mu}m$ BiCMOS process. The MOS-BJT derivative superposition (MBDS) technique exploits a parallel LC tank in the emitter of bipolar transistor to reduce the second-order non-linear coefficient ($g_{m2}$) which limits the enhancement of linearity performance. Two feedback capacitances are used in parallel with the base-collector and gate-drain capacitances to adjust the phase of third-order non-linear coefficients of bipolar and MOS transistors to improve the linearity characteristics. The MBDS technique is also employed cascode configuration to further reduce the second-order nonlinear coefficient. The proposed LNA exhibits gain of 9.3 dB and noise figure (NF) of 2.3 dB at 2 GHz. The excellent IIP3 of 20 dBm and low-power power consumption of 5.14 mW at the power supply of 1 V are achieved. The input return loss ($S_{11}$) and output return loss ($S_{22}$) are kept below - 10 dB and -15 dB, respectively. The reverse isolation ($S_{12}$) is better than -50 dB.