• Title/Summary/Keyword: LASAR

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Fault Detection through the LASAR Component modeling of PLD Devices (PLD 소자의 LASAR 부품 모델링을 통한 고장 검출)

  • Pyo, Dae-in;Hong, Seung-beom
    • Journal of Advanced Navigation Technology
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    • v.24 no.4
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    • pp.314-321
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    • 2020
  • Logic automated stimulus and response (LASAR) software is an automatic test program development tool for logic function test and fault detection of avionics components digital circuit cards. LASAR software needs to the information for the logic circuit function and input and output of the device. If there is no component information, normal component modeling is impossible. In this paper, component modeling is carried out through reverse design of programmable logic device (PLD) device without element information. The developed LASAR program identified failure detection rates through fault simulation results and single-seated fault insertion methods. Fault detection rates have risen by 3% to 91% for existing limited modeling and 94% for modeling through the reverse design. Also, the 22 case of stuck fault with the I/O pin of EP310 PLD were detected 100% to confirm the good performance.

Fault Detection System by the Extracting the ROM's Data (ROM 데이터 추출을 통한 결함검출 시스템)

  • Jeong, Jong-Gu;Jie, Min-Seok;Hong, Gyo-Young;Ahn, Dong-Man;Hong, Seung-Beom
    • Journal of the Korean Society for Aviation and Aeronautics
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    • v.19 no.4
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    • pp.18-23
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    • 2011
  • Generally, the digital circuit card can be tested by automatic test equipment using LASAR(Logic Automated Stimulus and Response). This paper proposes the ROM data extracting algorithm which can test the digital circuit card that consists usually ROMs. We are implemented of the proposed fault detecting program by LabWindow/CVI 8.5 and the digital automatic test instrument with NI-VXI(National Instrument - Versa Bus Modular Europe eXtentions for Instrumentation) card. We also make an interface circuit board connecting the digital test instrument and the digital circuit card. It shows the good performance of getting the data from ROMs.

A Study of Efficiency Improvement of the D-algorithm for NAND Circuits (NAND회로망의 시험패턴발생을 위한 D-알고리듬의 효율개선에 관한 연구)

  • 노정호;강병욱;안광선
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.7
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    • pp.734-745
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    • 1988
  • In this paper, it is tried to improve efficiency of the D-algorithm by assigning the logic values effectively on the nodes related to the critical path for back tracing to reduce the number of search nodes when acyclic combinational logic circuits are composed of NAND gates only. For that purpose, LASAR algorithm which is suitable for determining a critical path for back tracing is applied to the D-algorithm and it is implemented by IBM-PC with APL language. The test results on a number of NAND circuits which have multi-fanout, reconvergent and symetric characteristics show that the modified D-algorihtm reduces the number of search nodes in forward and backward tracing and decreases the run time of CPU about 10 percents.

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Risk of Recrudescence of Lymphatic Filariasis after Post-MDA Surveillance in Brugia malayi Endemic Belitung District, Indonesia

  • Santoso, Santoso;Yahya, Yahya;Supranelfy, Yanelza;Suryaningtyas, Nungki Hapsari;Taviv, Yulian;Yenni, Aprioza;Arisanti, Maya;Mayasari, Rika;Mahdalena, Vivin;Nurmaliani, Rizki;Marini, Marini;Krishnamoorthy, K.;Pangaribuan, Helena Ullyartha
    • Parasites, Hosts and Diseases
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    • v.58 no.6
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    • pp.627-634
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    • 2020
  • Belitung district in Bangka-Belitung Province, Indonesia with a population of 0.27 million is endemic for Brugia malayi and 5 rounds of mass drug administration (MDA) were completed by 2010. Based on the results of 3 transmission assessment surveys (TAS), the district is declared as achieving elimination of lymphatic filariasis (LF) in 2017. The findings of an independent survey conducted by the National Institute of Health Research and Development (NIHRD) in the same year showed microfilaria (Mf) prevalence of 1.3% in this district. In 2019, NIHRD conducted microfilaria survey in 2 villages in Belitung district. Screening of 311 and 360 individuals in Lasar and Suak Gual villages showed Mf prevalence of 5.1% and 2.2% with mean Mf density of 120 and 354 mf/ml in the respective villages. Mf prevalence was significantly higher among farmers and fishermen compared to others and the gender specific difference was not significant. The results of a questionnaire based interview showed that 62.4% of the respondents reported to have participated in MDA in Lasar while it was 57.7% in Suak Gual village. About 42% of the Mf positive cases did not participate in MDA. Environmental surveys identified many swampy areas supporting the breeding of Mansonia vector species. Persistence of infection is evident and in the event of successful TAS3 it is necessary to monitor the situation and plan for focal MDA. Appropriate surveillance strategies including xenomonitoring in post-MDA situations need to be developed to prevent resurgence of infection. Possible role of animal reservoirs is discussed.

A Study on the Fault Detection of ASIC using Dynamic Pattern Method (Dynamic Pattern 기법을 이용한 주문형 반도체 결함 검출에 관한 연구)

  • Shim, Woo-Che;Jung, Hae-Sung;Kang, Chang-Hun;Jie, Min-Seok;Hong, Gyo-Young;Ahn, Dong-Man;Hong, Seung-Beom
    • Journal of Advanced Navigation Technology
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    • v.17 no.5
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    • pp.560-567
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    • 2013
  • In this paper, it is proposed the fault detection method of the ASIC, without the Test Requirement Document(TRD), extracting internal logic circuit and analyzed the function of the ASIC using the multipurpose development program and simulation. If there don't have the TRD, it is impossible to analyze the operation of the circuit and find out the fault detection in any chip. Therefore, we make the TRD based on the analyzed logic data of the ASIC, and diagnose of the ASIC circuit at the gate level through the signal control of I/O pins using the Dynamic Pattern signal. According to the experimental results of the proposed method, we is confirmed the good performance of the fault detection capabilities which applied to the non-memory circuit.