• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.1
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• pp.23-28
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• 2008

In this paper, transient characteristics of the Punch Through Insulated Gate Bipolar Transistor (PT-IGBT) have been studied. On the contrary to Non-Punch Through Insulated Gate Bipolar Transistor(NPT-IGBT), it has a buffer layer and reduces switching power loss. It has a simple drive circuit controlled by the gate voltage of the MOSFET and low on-state resistance of the bipolar junction transistor. The transient characteristics of the PT-IGBT have been analyzed analytically. Excess minority carrier and charge distribution in active base region, the rate of anode voltage with time are expressed analytically by adding the influence of buffer layer. The experimental data is obtained from manufacturer. The theoretical predictions of the analysis have been compared with the experimental data obtained from the measurement of a device(600 V, 15 A) and show good agreement.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.351-354
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• 1998

In this paper, electrical characteristics of an n-channel Si MOSFET with L$_{s}$=0.6.mu.m under optical illumination are charaterized on wafer. Energetic photons with .gamma.=830nm, hv=1.494eV, P$_{opt}$=300mW are injected near the drain junction, the most photoresponsive region in the device, via optical fiber. We observed significantly increased drain current and transconductance, which is considered to be useful for the implementation of OEICs on silicon substrate, under optical control with P$_{opt}$=300mW. Optical power-dependent physical mechanisms responsible for the variation of electrical characteristics under optical input are also reported.d.d.d.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.10
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• pp.41-50
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• 1993

This paper describes the fabrication process and electrical characteristics of PSA (Polysilicon Self-Align) bipolar transistors with a thin base width of 1100.angs.. To realize this shallow junction depth, one-step rapid thermal annealing(RTA) technology has been applied instead of conventional furnace annealing process. It has been shown that the series resistances and parasitic capacitances are significantly reduced in the device with emitter area of 1${\times}4{\mu}m^{2}$. The switching speed of 2.4ns/gate was obtained by measuring the minimum propagation delay time in the I$^{2}$L ring oscillator with 31 stages.

• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.3
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• pp.22-26
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• 1974

The effects of anisotropic mechanical stress applied normal to the surface of p-n junctions have been investigated. As the stress increased, the breakdown voltage was decreased and the breakdown mode became softer. Within a certain limitation in the applied stress, the above phenomena werw reversibbe, though relaxation and hysteresis phenomena were observed. The time constant of relaxation depended upon the shape of the stressing tip, but for the given tip and device a unique time constant was obtained. The stress.dependence of breakdown voltage showed a good linearity up to about 3.0${\times}10^4$ kgw/$\textrm{cm}^2$, when the flat tip of radius 15$\mu$ was used, and the temperatere-dependence of breakdown voltage under the stress also showed a good linearity in the temperature range of 100 to $300^{\circ}K$.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1442-1444
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• 2001

A new low-temperature poly-Si TFT employing a counter-doped lateral body terminal is proposed and fabricated, in order to enhance the stability of poly-Si TFT driving circuits. The LBT structure effectively suppresses the kink effect by collecting the counter-polarity carriers and suppresses the hot carrier effect by reducing the peak lateral field at the drain junction. The proposed device is immune to dynamic stress, so that it is suitable for low voltage and high speed driving circuits of AMLCD.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.104-109
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• 2008

A simple and efficient way of modeling backgating in GaAs MESFET's is presented through depletion width modulation of Schottky junction and channel-substrate interface. It is shown semi-empirically that such a modulation of depletion widths causes serious troubles in designing precision circuits since backgating drastically reduces threshold voltage of MESFET as well as drain current. Finally, some of the results are compared with reported experimental results. This model may serve as a starting point for rigorous characterization of backgating effect on various device parameters of GaAs MESFET's.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.111-118
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• 1995

The three-dimentional effects on the breakdown voltage of non-reachthrough planar junctions which have the finite lateral radius of window curvature are analytically investigated. The critical electric fields at breakdown and the breakdown voltages are expressed successfully in a form which is normalized to the parallel plane case. The analytical results are in excellent agreement with the published results of experiment and the quasi-three-dimensional device simulation by MEDICI for non-reachthrough plane junctions having different background doping and junction depth. The results may be applicable to the estimations of breakdown voltages in many practical power devices.

• Journal of electromagnetic engineering and science
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• v.13 no.3
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• pp.165-172
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• 2013

This paper describes a design for a spiral antenna with a conical wall to obtain the high gain. The gain and the axial ratio of the spiral antenna were improved by a new design that included a conical wall and an optimized Archimedean slit on the ground plane in a conventional antenna with a circular cavity wall and a 4.5-turn slit. A gain improvement of 9.5 dBi higher and a good axial ratio of 1.9 dB lower were measured by the added conical wall and the newly designed slit from the current distribution control on the ground plane, respectively. The measured return loss, gain and axial ratio of the proposed antenna showed a good agreement with the simulated results. The proposed antenna will be applied to a non-linear junction detector system.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.136-143
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• 1996

A simple analytic model for the planar junctions with multiple foating field limiting rings(FLR) is presented which yields analytic expressions for the breakdown voltage and optimum ring spacings. the normalized potential of each ring is derived as a function of the normalized depletion width and the ring spacing. Based on the assumption that the breakdwon occurs simulataneously at cylindrical junctions of FLR structure where the peak sruface electric fields are equal, the optimum ring spacings are determined. The resutls are in good agreement with the simulations obtained from two dimensional device simulation program MEDICI and with the experimental data reported. The normalized experessions allow a calculation of breakdown voltage and optimum spacing over a broad range of junction depth and background doping levels.

• Journal of the Korea Society for Simulation
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• v.17 no.2
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• pp.13-19
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• 2008

New Buffered deposition is proposed to decrease junction electric field in this paper. Buffered deposition process is fabricated after first gate etch, followed NM1 ion implantation and deposition & etch nitride layer. New Buffered deposition structure has buffer layer to decrease electric field. Also we compared the hot carrier characteristics of Buffered deposition and conventional. Also, we design a test pattern including NMOSFET, PMOSFET, LvtNMOS, High pressure N/PMOSFET, so that we can evaluate DC/AC hot carrier degradation on-chip. As a result, we obtained 10 years hot carrier life time satisfaction.