• ETRI Journal
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• v.34 no.1
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• pp.44-54
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• 2012

Because of the intrinsic lack of internal-system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on-chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run-stop-type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG-based scanning operation. We apply this on-chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.

• ETRI Journal
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• v.35 no.2
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• pp.301-310
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• 2013

Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core's internal state has not been easy. Therefore, multicore processor debugging is very difficult and time-consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on-chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run-stop mode debugging. Compared with the debug architecture that supports the run-stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on-chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.50-61
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• 2010

Nowadays, the SoC is watched by all over the world with interest. The design trend of the SoC is hardware and software co-design which includes the design of hardware structure in RTL level and the development of embedded software. Also the technology is toward deep-submicron and the observability of the SoC's internal state is not easy. Because of the above reasons, the SoC debug is very difficult and time-consuming. So we need a reliable debugger to find the bugs in the SoC and embedded software. In this paper, we developed a hardware debugger named OCD. It is based on IEEE 1140.1 JTAG standard. In order to verify the operation of OCD, it is integrated into the 32bit RISC processor - Core-A (Core-A is the unique embedded processor designed by Korea) and is tested by interconnecting with software debugger. When embedding the OCD in Core-A, there is 14.7% gate count overhead. We can modify the DCU which occupies 2% gate count in OCD to adapt with other processors as a debugger.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2002.11a
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• pp.283-286
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• 2002

디지털 방송 시대를 맞아 별도의 테이프 없이 방송프로그램을 24시간 이상 녹화할 수 있는 개인용 비디오 녹화기에 대한 관심이 높아지고 있다. 본 논문에서는 인텔사의 스트롱암 프로세서(SA-1110)를 이용하여 임베디드 시스템을 구현하고 하드디스크드라이브를 연결하고 운영체제로 리눅스를 사용하여 PVR(Personal Video Recorder)용 하드디스크드라이브를 내장한 임베디드 시스템을 구현하였다. 본 논문에서는 플래시 메모리에 부트로더, 리눅스커널과 램디스크를 JTAG을 통해서 저장하고 스트롱암프로세서에서 리눅스 운영체제를 통하여 외부 인터페이스를 제어하게 된다. 치부 인터페이스로는 이더넷과 시리얼 통신을 제공한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.323-331
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• 2013

There are three ways how to extract forensic evidence from mobile phone, such as SYN, JTAG, Revolving. However, it should be a different way to extract forensic evidence due to the differences of their usage and technology between them(mobile phone and smart phone). Therefore, in this paper, I will come up with extraction method that forensics evidence by search and seizure of a smart phone. This study aims to analyze specifications and O.S., backup analysis, evidence in smart to analyze for search and seizure of a smart phone commonly used google android and windows mobile smart phone. This study also aim to extract forensics evidence related to google android and phone book, SMS, photos, video of window mobile smart phone to make legal evidence and forensics report. It is expected that this study on smart phone forensics technology will contribute to developing mobile forensics technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.281-284
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• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.235-239
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• 2010

Use of mobile phones reached saturation point, the recent use of the iPhone, including the Smart Phone is increasing rapidly. How to extract forensic data from current mobile phones and SYN, JTAG, Revolving There are three ways. Mobile phone and Smart Phone, but the technology and how to use forensic data because of the difference must have different extraction methods. In this paper, in the Smart Phone will study how to extract forensic data. Commonly used in the Google Android Smart Phone and Windows Mobile Smart Phone OS in the specification and analysis for analysis, the data analysis. Also, Google Android and Windows Mobile Smart Phone to extract forensic data to generate evidence. The present study tested the Mobile Smart Phone technology research will contribute to the development of forensic techniques.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.258-260
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• 2004

The Controller Area Network (CAN) is being widely used in real-time control applications such as automobiles, aircraft, and automated factories. Unfortunately, CAN, in its current form, is not able to either share out the system bandwidth among the different devices fairly or to grant an upper bound on the transmission times experienced by the nodes connected to the communication medium as it happens, for instance, in the token-based networks. In this paper, we present An Application Layer Design for Humanoid Robot in the CAN. Besides introducing the new algorithm, this paper also presents some performance figures obtained using a specially developed software simulator and experimentation for composition of CAN which uses JTAG mode of a parallel debugging., while the behavior of the new algorithm is compared with the traditional CAN systems. in order to see how effective they are.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09a
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• pp.58-61
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• 2003

This paper proposes e-Learning environments far digital circuit experiment. The e-Learning environments are implemented as a WBT system that includes the circuits monitoring system and the students management system. In the WBT client-server system, the instructor represents the server and students represent clients. The client computers are equipped with a digital circuit training board and connected to the server on the World Wide Web. The training board consists of a Programmable Logic Device (PLD) and measuring instruments. The instructor can reconfigure the PLD with various circuit designs from the server so that students can investigate signals from the training board. The instructor can monitor the progress of the students using Joint Test Action Grouo(JTAG) technology. We implement the WBT system and a courseware fo digital circuits and evaluation the environments.

• Proceedings of the Korean Society of Computer Information Conference
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• 2011.06a
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• pp.191-195
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• 2011

Smart Phone의 OS로 많이 사용하는 Android/Windows Mobile Smart Phone의 사용이 급격히 증가하고 있다. 무료 WiFi Zone과 인터넷 사용에 대한 취약점이 존재한다. Mobile Forensic의 증거 자료를 추출하는 방법은 SYN, JTAG, Revolving 방법이 있지만, 기존 휴대폰과 달리 Smart Phone은 OS와 구조, 사용방식과 기술의 차이로 인한 Mobile Forensic 연구 방법도 달라야 한다. 본 논문에서는 Smart Phone에서는 많이 사용되는 Windows Mobile/Android Smart Phone의 OS와 구조 차이를 분석한 데이터 백업과 스펙 분석 및 증거자료 분석을 한다. 또한 무료 WiFi Zone을 통한 인터넷 사용시에 취약점을 분석한다. 그리고 Android/Windows Mobile Smart Phone의 Forensic 자료를 생성하여 증거를 추출하고, Mobile Forensic 보고서를 생성한다. 본 연구를 통하여 Mobile Forensic의 기술 발전에 초석을 제공할 것이다.