• Journal of Power Electronics
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• v.16 no.1
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• pp.48-56
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• 2016

This paper proposes a method for detecting irreversible demagnetization using the harmonic analysis of back electromotive force (BEMF) in interior permanent magnet-type brushless DC motors. First, demagnetization patterns, such as equality, inequality, and weighted demagnetizations, are defined and classified by considering the possibility of demagnetization resulting from motor operating characteristics. Second, an available diagnostic model for the harmonic analysis of BEMFs is defined according to pole-slot coefficients because the characteristics of BEMFs under demagnetization conditions are affected by the combination of poles and slots. Third, BEMFs and their harmonic components under normal and demagnetization conditions are analyzed through simulation and experiment to verify the proposed demagnetization detection technique.

• Journal of Power Electronics
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• v.15 no.1
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• pp.235-245
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• 2015

This paper proposes a reactive current assignment and control strategy for a doubly-fed induction generator (DFIG) based wind-turbine generation system under generic grid voltage sag or swell conditions. The system's active and reactive power constrains during grid faults are investigated with both the grid- and rotor-side convertors (GSC and RSC) maximum ampere limits considered. To meet the latest grid codes, especially the low- and high-voltage ride-through (LVRT and HVRT) requirements, an adaptive reactive current control scheme is investigated. In addition, a torque-oscillation suppression technique is designed to reduce the mechanism stress on turbine systems caused by intensive voltage variations. Simulation and experiment studies demonstrate the feasibility and effectiveness of the proposed control scheme to enhance the fault ride-through (FRT) capability of DFIG-based wind turbines during violent changes in grid voltage.

• Journal of Power Electronics
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• v.15 no.1
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• pp.78-85
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• 2015

This paper presents a new structure of single-stage flyback power factor correction (PFC) converter with a controllable coupled negative magnetic feedback (NMF) winding. NMF winding is used to reduce the bulk capacitor voltage at high line voltages and light loads. However, it would cause line current distortion at zero crossing condition. In the proposed circuit, a series winding is used with NMF inductor to eliminate the NMF inductor at low line voltages. As a result, the dead angle of the input current, near zero voltage crossing, is eliminated and the power factor is increased. The presented experimental results of the proposed PFC converter confirm the integrity of the new idea and the theoretical analysis.

• Journal of Power Electronics
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• v.15 no.1
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• pp.116-122
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• 2015

This paper presents a new current sharing control strategy for parallel-connected, synchronised three-phase DC-AC converters employing space vector pulse width modulation (SVPWM) without current sharing reactors. Unlike conventional control methods, the proposed method breaks the paths of the circulating current by dividing the switching cycle evenly between parallel connected equally rated converters. Accordingly, any inter-module reactors or circulating current control will be redundant, leading to reductions in system costs, size, and control algorithm complexity. Each converter in the new scheme employs a synchronous dq current regulator that uses only local information to attain a desired converter current. A stability analysis of the current controller is included together with a simulation of the converter and load current waveforms. Experimental results from a 2.5kVA test rig are included to verify the proposed control method.

• Journal of Power Electronics
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• v.15 no.1
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• pp.1-9
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• 2015

This study presents a novel transformer isolated parallel connected quasi Z-source (qZ-source) full-bridge DC-DC converter that uses a coupled inductor in both the qZ-source network and output filter inductor. Unlike traditional voltage-fed or current-fed converters, the proposed converter can be open- and short-circuited without damaging switching devices. Therefore, the desired buck and boost functions can be achieved and converter reliability can be significantly improved. All the bulky inductors in the qZ-source network and output filter can also be minimized with the proposed inductor structures. A 4 kW prototype DC-DC converter is built and tested to verify the performance of the proposed converter.

• Journal of Power Electronics
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• v.15 no.1
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• pp.39-53
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• 2015

This paper presents the regulation of the output voltage and inductor currents in a Single Ended Primary Inductor Converter (SEPIC), operating in the continuous conduction mode (CCM) using a sliding mode controller. Owing to the time varying nature of the SEPIC converter, designing a feedback controller is a challenging task. In order to improve the dynamic performance of the SEPIC, a Sliding Mode Controller (SMC) is developed. The developed SMC is designed by using a state space average model. The performance of the developed controller with the SEPIC converter is validated at different working conditions through Matlab simulations. It is also compared with the performance while using a PI controller. The results show that the designed controller gives very good output voltage regulation under different operating conditions such as a varying input voltage, changes in the load and component variations. A 48V, 46W experimental setup for has been developed in an analog platform to validate the performance of the proposed SMC.

• Journal of Power Electronics
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• v.16 no.1
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• pp.268-276
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• 2016

A hybrid sinusoidal-pulse current (HSPC) charging method for the Li-ion batteries in electric vehicle applications is proposed in this paper. The HSPC charging method is based on the Li-ion battery ac-impedance spectrum analysis, while taking into account the high power requirement and system integration. The proposed HSPC method overcomes the power limitation in the sinusoidal ripple current (SRC) charging method. The charger shares the power devices in the motor inverter for hardware cost saving. Phase shifting in multiple pulse currents is employed to generate a high frequency multilevel charging current. Simulation and experimental results show that the proposed HSPC method improves the charger efficiency related to the hardware and the battery energy transfer efficiency.

• Journal of Power Electronics
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• v.16 no.1
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• pp.310-318
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• 2016

This paper presents a new orthogonal signals generator (OSG) with DC Offset rejection for implementing a phase locked loop (PLL) in single-phase grid-connected power systems. An adaptive filter (AF) based on the least mean square (LMS) algorithm is used to constitute the OSG in this study. The DC offset in the measured grid voltage signal can be significantly rejected in the developed OSG technique. This generates two pure orthogonal signals that are free from the DC offset. As a result, the DC offset rejection performance of the presented single-phase phase locked loop (SPLL) can be enhanced. A mathematical model of the developed OSG and the principle of the adaptive filter based SPLL (AF-SPLL) are presented in detail. Finally, simulation and experimental results demonstrate the feasibility of the proposed AF-SPLL.

• Journal of Power Electronics
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• v.16 no.1
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• pp.173-181
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• 2016

In this paper, a new technique for harmonic optimization in cascaded H-bridge 7-level inverters is proposed. The suggested strategy is based on minimizing an objective function which simultaneously optimizes the converter utilization and Total Harmonic Distortion (THD). The Switch Utilization Ratio (SUR) is formulized for both the phase and line-line voltages of a 7-level inverter and is considered in the final objective functions. Based upon the SUR formula, utilization ratio enhancement will reduce the value of feeding DC links, which improves the efficiency and lifetime of the circuit components due to lower voltage stresses and losses. In order to achieve more effective solution in different modulation indices, it is assumed that the DC sources can be altered. Experimental validation is presented based on a three-phase 7-level inverter prototype.

• Journal of Power Electronics
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• v.16 no.1
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• pp.340-350
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• 2016

A cascaded hybrid multilevel inverter including a reconfiguration technique for low voltage dc distribution applications is proposed in this paper. A PWM generation fault detection and reconfiguration paradigm after an inverter cell fault are developed by using only a single-chip controller. The proposed PWM technique is also modified to reduce switching losses. In addition, the proposed topology can reduce the number of required power switches compared to the conventional cascaded multilevel inverter. The proposed technique is validated by using a 3-kVA prototype. The switching losses of the proposed multilevel inverter are also investigated. The experimental results show that the proposed hybrid inverter can improve system efficiency, reliability and cost effectiveness. The efficiency of proposed system is 97.45% under the tested conditions. The proposed hybrid inverter topology is a promising method for low voltage dc distribution and can be applied for the multiple loads which are required in a data center or telecommunication building.