A New Orthogonal Signal Generator with DC Offset Rejection for Single-Phase Phase Locked Loops

Abstract

This paper presents a new orthogonal signals generator (OSG) with DC Offset rejection for implementing a phase locked loop (PLL) in single-phase grid-connected power systems. An adaptive filter (AF) based on the least mean square (LMS) algorithm is used to constitute the OSG in this study. The DC offset in the measured grid voltage signal can be significantly rejected in the developed OSG technique. This generates two pure orthogonal signals that are free from the DC offset. As a result, the DC offset rejection performance of the presented single-phase phase locked loop (SPLL) can be enhanced. A mathematical model of the developed OSG and the principle of the adaptive filter based SPLL (AF-SPLL) are presented in detail. Finally, simulation and experimental results demonstrate the feasibility of the proposed AF-SPLL.

I. INTRODUCTION

Nowadays, a lot of single-phase power converters such as DC/AC converters, UPSs and active power filters are being connected to the utility grid. One of the most important features of their control strategies is to synchronize the power converters with the grid at the point of common coupling (PCC). To achieve this goal, grid voltage information such as the frequency and phase angle should be obtained in a rapid and precise way. At present, the single-phase phase locked loop (SPLL) technique is the most widely used method to estimate grid voltage information. In addition, the SPLL method can also be adopted to monitor the performance of grid-connected power systems [1].

The instant measurement of the grid voltage information in single-phase power systems is more difficult than that in three-phase balanced power systems where the three phase grid voltage vectors can be easily converted into two orthogonal variables. However, there is only one phase voltage signal available in single-phase systems. In order to mimic the three-phase power systems, an orthogonal signals generator (OSG) should be used to create an orthogonal signal for the single-phase grid voltage. Subsequently, it is possible to use existing PLL algorithms in three-phase power systems to estimate the grid voltage information in single-phase power systems.

In the past few years, various kinds of OSG techniques have been proposed in the literature. In [2] and [3], the orthogonal frame was created through the use of an inverse park transformation. This method is simple. However, the included low-pass filters reduce the synchronizing speed and degrade the dynamic performance. As pointed out in [4] and [5], it is feasible to use the Hilbert transformer to build the desired orthogonal frame. However, the Hilbert transformer suffers from instability because it is implemented with derivative operations. The transport delay block which introduces a 90 degrees phase shift was adopted in [6] and [7] to produce the orthogonal component. Although it is simple to implement, it suffers due to its lack of filtering capability and inaccuracies under frequency varying applications. The widely used second order generalized integrator (SOGI) generates the orthogonal signal with a band-pass filter and effectively attenuate the high order harmonic components [8]. It is worth mentioning that the SOGI is capable of filtering the input sinusoidal signal without introducing a phase delay. The all-pass filter method in [9] can obtain the orthogonal signal in a similar way but without causing attenuation on the high order harmonics. These two methods can produce an accurate orthogonal frame through feedback of the estimated grid frequency.

As an alternative, this paper presents a new OSG technique with a least mean square (LMS) algorithm based adaptive filter (AF). In the literature, adaptive filter technology has found application in PLL systems [10]-[13]. Since the adaptive filter has superior filtering capability, by letting the grid voltage signal pass through an adaptive filter before it is connected to the PLL, the resulting PLL systems can exhibit enhanced noise and harmonics rejection performance. However, the adaptive filter has seldom been used as an OSG. The AF based SPLL (referred to as OAF-SPLL in this paper) shown in Fig. 1 was analyzed in [12] and [13], where it has been shown to have some harmonic rejection capability due to the adopted AF. The AF was only used for its filtering characteristic. There is no evidence that the AF operates as an OSG in the OAF-SPLL. In this study, a mathematical model of the LMS based AF when imposed on a given sinusoidal signal is derived first. Then the developed OSG is introduced. It should be mentioned that the developed OSG exhibits DC offset rejection by integrating a simple integral loop. This is different from DC offset elimination loops based on the error between the input signal and the output in-phase signal proposed in [14] and [15]. Subsequently, the new AF-SPLL is proposed.

Fig. 1.The block diagram of the original adaptive filter based SPLL (OAF-SPLL).

This paper is organized as follows. Section II gives a description of the conventional SOGI-SPLL. The LMS based AF and the developed OSG are illustrated in Section III. Then, the proposed AF-SPLL is presented in Section IV. Experimental results are given in Section V. Finally, some conclusions are given in Section VI.

 

II. THE CONVENTIONAL SOGI-SPLL

A. Review of the SOGI-SPLL

Fig. 2 describes the widely used SOGI-SPLL. As shown in Fig. 2, a virtual orthogonal coordinate consisting of the in-phase signal Vα and the quadrature signal Vβ is created by using the SOGI. Then, αβ-pPLL is adopted for implementing the phase locked function based on the produced in-phase and quadrature components. It should be noted that the SOGI is dependent of the estimated frequency of αβ-pPLL to make it frequency adaptive. The gain K of the SOGI affects the dynamic response speed. It also has a great influence on the filtering performance of the SOGI. As stated in [8], a decrease of K results in a heavy filtering. However, at the same time the dynamic response becomes slower.

Fig. 2.The SOGI based αβ-pPLL (SOGI-SPLL).

Assume that the grid voltage is of the following form:

where Vgm represents the grid voltage amplitude, ωg denotes the grid frequency, φ is the initial grid voltage phase angle, and θ is the instantaneous phase angle. From Fig. 2, the transfer functions for generating the in-phase and orthogonal signals in the SOGI can be expressed as:

It follows from (2) that Wα (s) is a band-pass filter, while Wβ (s) is a low-pass filter. Thus, the generated α-axis and β-axis voltages in the SOGI can be written as:

Therefore, it follows from Fig. 2 that the input signal to the PI regulator of αβ-pPLL can be obtained by:

where is the estimated grid voltage phase angle. In normal operations, it follows from (5) that the first part goes to zero in the steady state as approaches θ . At the same time, the estimated grid frequency converges to the grid frequency. It should be mentioned that a DC offset may exist in the measured grid voltage due to the nonlinearity of the voltage sensors, the AD conversion process, and the thermal drift of the analogue components. The DC offset can propagate into the produced orthogonal signal Vβ because of the low-pass characteristic of Wβ (s) . This can cause low-frequency oscillations in the grid voltage estimation loops.

 

III. PROPOSED ORTHOGONAL SIGNALS GENERATOR

A. LMS Based Adaptive Filter

Fig. 3 depicts a block diagram of the proposed AF-SPLL, where the least mean square (LMS) algorithm is used to adjust the adaptive weights w1(n) and w2 (n) of the AF by minimizing the square of the error between the input signal and the output signal of the AF. The updating law of the weights w1(n) and w2 (n) based on the LMS algorithm can be expressed as:

where μ is the step size parameter of the AF. For simplicity, the gain parameter KDC of the DC offset elimination loop is set to zero when analyzing the AF. Its differential model can be derived from (6) as:

where Kc = μ / Ts , the sampling period is Ts , the input signal d(t) = Vg = Vgm sin(ωgt + φ) , and the input vector of the AF is:

It follows from (6) and (7) that the AF can be expressed with the state-space model as:

According to [16] and [17], the AF can be guaranteed to converge if the following condition is met:

Fig. 3.The block diagram of the proposed AF-SPLL.

It should be pointed out that formula (9) is a sufficient criterion for the convergence of the AF. In practice, (9) can be ensured by choosing 0 < μ < 1 .

As shown in (8), the presented AF is a linear time-variant system. According to the characteristics of linear time-variant systems, the instantaneous weight matrix W(t) can be written as:

Usually, it is difficult to calculate the analytical formulation of the state transition matrix Φ(t,0) in time-variant systems. Fortunately, as illustrated in [18], the transition matrix Φ(t,0) of time-variant systems can be expressed as (11) if A(t) is of the form eΩt Be-Ωt where Ω and B are constant matrices.

From (8), the state matrix A(t) of the AF can be rewritten as:

where:

Therefore, with any method for calculating the exponential matrix, it is possible to calculate the transition matrix Φ(t,0) as follows:

In which, a and b are the solutions of (15).

Without a loss of generality, a and b are assuming to be (16) if Kc ≥ ω .

It should be noted that a and b should be in complex form if Kc < ω . Considering the transitivity of Φ(t,0) , the following can be obtained:

Thus:

By the substitution of (18) into (10), the weight matrix W(t) can be obtained as:

Therefore, an accurate weight matrix W(t) in time domain can be derived as:

where ω1 = ωg - ω , ω2 = ωg + ω and the phase angle difference ε satisfies:

and the exponential decaying components in (20) are of the following form:

In the steady state, where the estimated angular frequency ω converges to the grid frequency ωg , it can be observed from (21) that the phase angle difference ε becomes zero. Without considering the negligible exponential decaying components in (20), the steady-state weights w1S (t) and w2S (t) can be achieved as:

Since the phase error (φ - δ) becomes zero in the steady state, the steady-state weights and the output yS (t) of the AF can be given by:

It can be seen from (23) that the output of the AF is identical to the input signal, and that w1 and w2 are the amplitude of input signal and zero in the steady state, respectively. When w2 converges to zero, the input to the DC offset elimination loop also becomes zero in Fig. 3. As a result, the DC offset elimination loop has no influence on the steady-state performance of the presented AF-SPLL in this scenario. Assuming that the input signal of the AF is a pure DC signal as d(t) = d , the steady-state weights w1S (t) and w2S (t) can be achieved from (20) as:

Thus, the output of the DC offset elimination loop can be given by:

It is clear that the output signal VDC increases until it remains constant at the value of a pure input DC signal d . In other words, the DC offset elimination loop can be used to remove the DC offset of the input signal before it entering into the AF.

B. Proposed Orthogonal Signals Generator

In this study, the developed OSG method is implemented as follows:

Considering that the grid voltage contains a DC offset as Vg = Vgm sin(ωgt + φ) + d , according to (22) and (24), the instantaneous in-phase signal Vα and the orthogonal signal Vβ can be rewritten as:

As mentioned above, the phase angle difference ε becomes zero once the estimated grid frequency ω approaches the grid frequency ωg in the steady state. Consequently, in the steady state, (27) can be represented by:

It can be found from (28) that the in-phase signal Vα matches well with the input signal, and that the orthogonal signal Vβ lags behind the in-phase signal Vα by exactly 90 degrees. In addition, both the in-phase and orthogonal signals are free from DC offset. Namely, the proposed OSG technique can generate a virtual orthogonal coordinate from the single-phase grid voltage while significantly rejecting the DC offset.

 

IV. PROPOSED AF-SPLL

A. Principle Description

Fig. 3 depicts a block diagram of the proposed AF-SPLL approach, which is comprised of an AF based OSG and a αβ-pPLL block. The AF based OSG produces in-phase and orthogonal components from the available grid voltage signal while maintaining the DC offset rejection performance. Based on the created orthogonal signals, both the grid voltage frequency and the phase angle are estimated in the αβ-pPLL block.

B. αβ-pPLL

It can be seen from Fig. 3 that the input signal ep to the PI unit of αβ-pPLL is determined by:

Thus, substitution of (27) into (29) yields:

It follows from (30) that the error ep converges to zero only when the estimated grid frequency ω and phase angle (ωt + δ ) approach the actual grid frequency ωg and phase angle (ωgt + φ ), respectively.

 

V. EXPERIMENTAL DISCUSSION

To evaluate the presented AF-SPLL, several simulations have been implemented and the simulation results are discussed below. In addition, the AF-SPLL is compared with the conventional SOGI-SPLL under different conditions. The key parameters of the SOGI-SPLL and AF-SPLL are listed in Table I. The gain K of the SOGI is set to 1.55 for the fastest dynamic response, and the step size parameter μ is set to 0.025. In order to make a comparison under the same conditions, the proportional and integral parameters of the PI unit in both the SOGI-SPLL and the AF-SPLL are chosen to be the same. They are 0.493 and 19 to achieve a settling time of 0.06 s and a unitary damping factor [8].

TABLE ISPECIFICATIONS OF SPLLS

In order to further validate the feasibility of the AF-SPLL, several experiments were implemented. The experimental setup, as shown in Fig. 4, has one integrated circuit board. The developed AF-SPLL was implemented on a DSP (TMS320F28335). For the purpose of comparison, a SOGI-SPLL was also tested on the same DSP. All of the realizations operated at a 10 kHz sampling frequency.

Fig. 4.Experimental setup.

A. Dynamic Response to a 2 Hz Frequency Jump

To test the dynamic performance of the proposed AF-SPLL to grid frequency jumps, a 2 Hz frequency jump was triggered as depicted in Fig. 5. It can be seen from Fig. 5(a) that the AF-SPLL tracks the changed grid frequency in about 30ms, that and the SOGI-SPLL spends nearly the same amount of time to finish the grid frequency estimation as shown in Fig. 5(b).

Fig. 5.Grid frequency jumps from 50Hz to 52Hz.

B. Dynamic Response to a 30 Degree Phase Jump

Then, comparative tests were carried out to test the dynamic performance of the AF-SPLL and SOGI-SPLL with respect to grid voltage phase jumps. A 30 degree phase jump was stimulated, and the corresponding results are depicted in Fig. 6. As shown in Fig. 6(a) and Fig. 6(b), both the AF-SPLL and SOGI-SPLL can obtain accurate grid frequency and phase in about 40 ms.

Fig. 6.Grid voltage phase jumps to 30 degrees from zero.

C. Dynamic Response to a Grid Voltage Sag

To evaluate the dynamic response of the AF-SPLL and SOGI-SPLL to a grid voltage sag, a 30V drop in the grid voltage amplitude was tested, and the experimental results are illustrated in Fig. 7. It can be seen that the estimated grid frequency converges to the steady-state value and that the phase angle estimation error becomes zero in about 40ms in both the AF-SPLL and the SOGI-SPLL. In fact, the AF-SPLL and SOGI-SPLL give nearly the same response to a grid voltage sag.

Fig. 7.Grid voltage amplitude drops to 260V from 311V.

D. DC Offset Rejection

10V DC offset is artificially added into the grid voltage signal to investigate the DC offset rejection performance of AF-SPLL and SOGI-PLL, and the according results are described in Fig. 8. It can be seen from Fig. 8(a) that both the frequency error and the phase error converge to zero after about 60 ms in AF-PLL. However, it is shown in Fig. 8(b) that SOGI-PLL suffers from periodical oscillations in both the grid frequency and phase estimations after the DC offset is added.

Fig. 8.10 V DC offset is added into the measured grid voltage.

E. Harmonics Rejection

To compare the performance of harmonic suppression, a total 5% harmonic (3.2% 5rd and 1.8% 7th) was added to the measured grid voltage, and the corresponding results are described in Fig. 9. It follows from Fig. 9 that both the AF-SPLL and the SOGI-SPLL cannot totally reject the added harmonic, and that the estimated grid frequency and phase contain distortions. It should be mentioned that other SPLLs with enhanced harmonic rejection capability should be used instead of the AF-SPLL or the SOGI-SPLL in seriously distorted applications, or more work should be done to improve the harmonic rejection performance of the AF-SPLL and the SOGI-SPLL.

Fig. 9.5% total harmonics are added.

F. Summary Sheet

Table II shows a comparison of the AP-PLL and the SOGI-PLL in the different conditions shown above. From this comparison it is known that the proposed AF-PLL has similar performance under most general grid voltage distortions. In addition, the conventional SOGI-PLL has a little better performance under the condition of a voltage sag. However, it cannot reject the DC offset in the grid voltage. The proposed OSG based AF shows its feasibility in PLL applications.

TABLE IICOMPARISON OF SPLLS

 

VI. CONCLUSIONS

A new AF based OSG structure is proposed in this paper. It is discussed in detail together with the working principle of the newly built AF-SPLL. Firstly, a mathematical model of the LMS based AF is derived in the time domain. Subsequently, the proposed OSG technique and a DC offset elimination strategy are introduced. Finally, the AF-SPLL is tested on a laboratory experimental setup and is compared with the conventional SOGI-SPLL. All of the experimental results demonstrate the feasibility of both the presented OSG technique and the AF-SPLL.