• 전자공학회논문지A
• /
• 제28A권9호
• /
• pp.743-751
• /
• 1991

This paper presents the 1.5\ulcorner PSA bipolar device which establishes the performance improvement such as the reduction of emitter resistance and substrate junction capacitance. To achieve the above electrical characteristics, RTA process and trench isolation technology were adapted. The emitter resistance and substrate capacitance of npn transistor having 1.5$[\times}6{\mu}m^{2}$emitter area was measured with 63$\Omega$and 28fF, respectively. The minimum propagation delay time shows 121ps at 0.7mW from the measurement of 31 stage ring oscillator.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2000년도 하계학술대회 논문집
• /
• pp.759-762
• /
• 2000

Present transistors which have vertical structure show increased parasitic capacitance characteristics in accordance with the increase of non-active base area and collector area, consequently have disadvantage for high speed switching performance. In this paper, a horizontal structure transistor which has minimized parasitic capacitance in virtue of SDB(Silicon Direct Bonding) wafer and oxide sidewall isolation utilizing silicon trench technology is presented. Its structural characteristics were designed by ATHENA(SUPREM4), the process simulator from SILVACO International, and its performance was proven by ATLAS, the device simulator from SILVACO International. The performance of the proposed horizontal structure transistor was certified through the VCE-lC characteristics curve, $h_{FE}$ -IC characteristics, and GP-plot.

• 한국컴퓨터산업교육학회:학술대회논문집
• /
• 한국컴퓨터산업교육학회 2003년도 제4회 종합학술대회 논문집
• /
• pp.67-70
• /
• 2003

In this paper, propose a new structure of MOFET(Metal-Oxide-Semiconductor Field Effect Transistor) which is widely application for semiconductor technologies. Eleminate the latch-up effect caused by closed devices when conpose a electronic circuit using proposed devices. In this device have a completely isolation structure, and advantage of leakage current elimination. Each independent devices are isolated by trench-well and oxide layer of SOI substrate. Using trench gate and self aligned techniques reduces parasitic capacitance between gate and source, drain. In this paper, we proposed the new structure of SOI MOSFET which has completely isolation and contains trench gate electrodes and SOI wafers. It is simulated by MEDICI that is device simulator.

• 대한전자공학회논문지SD
• /
• 제41권3호
• /
• pp.109-114
• /
• 2004

본 논문에서는 반도체 방식의 직접 터치식 용량 형 지문인식센서의 신호처리를 위한 회로를 제안하였다. 센서로부터의 용량의 변화를 전압의 신호로 전환하기 위해서 전하분할 방식의 회로를 적용하였다. 지문센서 감도저하의 가장 큰 원인인 센서 플레이트에 존재하는 기생용량을 제거하고 융선과 계곡 사이의 전압차를 향상시키기 위하여 기존과는 다른 아날로그 버퍼회로를 설계 적용하였다. 센서 하부회로와의 isolation 대책을 통하여 ESD 및 노이즈방지를 위한 설계를 실시하였다. 제안된 신호 처리회로는 0.35마이크론 표준 CMOS 공정에 의해 레이아웃 되었다.

• Transactions on Electrical and Electronic Materials
• /
• 제17권4호
• /
• pp.183-188
• /
• 2016

This paper presents the design and characterization of wide band ohmic microswitch with an actuation voltage as low as 20~25 V, and a restoring force of 14.1 μN. The design of the proposed switch is primarily composed of an electrostatic actuator, bridge membrane, cantilever (beam) and coplanar waveguide, suspended over the substrate. The analysis shows an insertion loss of −0.002 dB at 1GHz and remains as low as −0.35 dB, even at 100 GHz. The isolation loss of the switch is sustained at −21.09 dB at 100GHz, with a peak value of −99.58 dB at 1 GHz and up-state capacitance of 4 fF. To our knowledge, this is the first demonstration of a series contact switch, which works over a wide bandwidth (DC-100 GHz) and with such a high and sustained isolation, even at high frequencies and with an excellent figure of merit (f_c=1/2.pi.Ron.Cu= 39.7 THz).

• 한국항행학회논문지
• /
• 제18권1호
• /
• pp.56-66
• /
• 2014

태양광 발전에 있어서 태양전지는 일사량, 온도와 부하에 의해 크게 변동하기 때문에 태양전지에 대한 특성 해석이 필요하다. 또한 태양광 발전에 있어서 가능한 많은 에너지를 얻기 위해서는 환경변화에 따른 태양의 위치추적이 필요하며 태양전지의 출력을 항상 최대로 제어할 필요가 있다. 센서와 마이크로프로세서 칩으로 구현된 본 시스템의 실험 결과는 Boost 컨버터의 승압율은 167[%], 소용량에서 에너지 Harvesting 개념과 위치추적 방식의 태양광 발전 구현 가능성을 제시하였다.

• Transactions on Electrical and Electronic Materials
• /
• 제5권5호
• /
• pp.169-172
• /
• 2004

Deep sub-micron device required to get the superior ultra thin gate oxide characteristics. In this research, I will recommend a novel shallow trench isolation structure(STI) for thin gate oxide and a $N_2$O gate oxide 30 $\AA$ by NO ambient process. The local oxidation of silicon(LOCOS) isolation has been replaced by the shallow trench isolation which has less encroachment into the active device area. Also for $N_2$O gate oxide 30 $\AA$, ultra thin gate oxide 30 $\AA$ was formed by using the $N_2$O gate oxide formation method on STI structure and LOCOS structure. For the metal electrode and junction, TiSi$_2$ process was performed by RTP annealing at 850 $^{\circ}C$ for 29 sec. In the viewpoints of the physical characteristics of MOS capacitor, STI structure was confirmed by SEM. STI structure was expected to minimize the oxide loss at the channel edge. Also, STI structure is considered to decrease the threshold voltage, result in a lower Ti/TiN resistance( Ω /cont.) and higher capacitance-gate voltage(C- V) that made the STI structure more effective. In terms of the TDDB(sec) characteristics, the STI structure showed the stable value of 25 % ～ 90 % more than 55 sec. In brief, analysis of the ultra thin gate oxide 30 $\AA$ proved that STI isolation structure and salicidation process presented in this study. I could achieve improved electrical characteristics and reliability for deep submicron devices with 30 $\AA$ $N_2$O gate oxide.

• 대한전자공학회논문지TC
• /
• 제42권7호
• /
• pp.57-62
• /
• 2005

본 논문에서는 마이크로파 SPDT 스위치를 GaAs pHEMT 공정을 이용하여 설계 및 제작하였다. 광대역 스위치 설계를 위하여 CPW로 구현한 임피던스 변환회로를 삽입하여 온-저항과 오프-커패시턴스를 줄임으로서 낮은 삽입손실과 높은 격리도를 갖는 구조를 구현하였다. 변환회로를 구성하는 전송선로의 소자 개수와 병렬로 삽입되는 FET의 개수는 시물레이션을 통해 최적의 값으로 설계하였다. 설계된 스위치의 측정 결과 53$\~$ 61 GHz 대역에서 2.6 dB 이하의 삽입손실과 24 dB 이상의 격리도를 얻었다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제14권4호
• /
• pp.427-435
• /
• 2014

Segmented-channel MOSFETs (SegFETs) can achieve both good performance and variation robustness through the use of $HfO_2$ (a high-k material) to create the shallow trench isolation (STI) region and the very shallow trench isolation (VSTI) region in them. SegFETs with both an HTI region and a VSTI region (i.e., the STI region is filled with $HfO_2$, and the VSTI region is filled with $SiO_2$) can meet the device specifications for high-performance (HP) applications, whereas SegFETs with both an STI region and a VHTI region (i.e., the VSTI region is filled with $HfO_2$, and the STI region is filled with $SiO_2$) are best suited to low-standby power applications. AC analysis shows that the total capacitance of the gate ($C_{gg}$) is strongly affected by the materials in the STI and VSTI regions because of the fringing electric-field effect. This implies that the highest $C_{gg}$ value can be obtained in an HTI/VHTI SegFET. Lastly, the three-dimensional TCAD simulation results with three different random variation sources [e.g., line-edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV)] show that there is no significant dependence on the materials used in the STI or VSTI regions, because of the predominance of the WFV.

• Journal of Power Electronics
• /
• 제13권2호
• /
• pp.177-185
• /
• 2013

This paper studies a soft switching DC/DC converter to achieve zero voltage switching (ZVS) for all switches under a wide range of load condition and input voltage. Two three-level PWM circuits with the same power switches are adopted to reduce the voltage stress of MOSFETs at $V_{in}/2$ and achieve load current sharing. Thus, the current stress and power rating of power semiconductors at the secondary side are reduced. The series-connected transformers are adopted in each three-level circuit. Each transformer can be operated as an inductor to smooth the output current or a transformer to achieve the electric isolation and power transfer from the input side to the output side. Therefore, no output inductor is needed at the secondary side. Two center-tapped rectifiers connected in parallel are used at the secondary side to achieve load current sharing. Due to the resonant behavior by the resonant inductance and resonant capacitance at the transition interval, all switches are turned on at ZVS. Experiments based on a 1kW prototype are provided to verify the performance of proposed converter.