• 전기학회논문지
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• 제59권9호
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• pp.1615-1620
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• 2010

A thin film thermoelectric cooler for COB direct assembly was proposed and the COB cooler structure was modeled by electrical equivalent circuit by using SPICE model of thermoelectric devices. The embedded cooler attached between the die chip and metal plate can offer the possibility of thin film active cooling for the COB direct assembly. We proposed a driving method of TEC by using pulse width modulation technique. The optimum power to the TEC is simulated by using a SPICE model of thermoelectric device and passive components representing thermal resistance and capacitance. The measured and simulated results offer the possibility of thin film active cooling for the COB direct assembly.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 D
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• pp.3019-3021
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• 2005

In this paper we suggest a novel temperature detection method utilized in direct over-temperature protection circuit modeling. The suggested model detects temperature variation using Rds(on) characteristics of MOSFET, while the conventional methods are using extra devices such as a temperature sensor or an over-temperature detection transistor. The temperature-dependant MOSFET model is implemented using Spice ABM(Spice Analog Behavior Model). The direct over-temperature protection circuit was designed including it. We verified effectiveness of the temperature dependant Rds(on) model characteristics and performance of the direct over-temperature protection circuit on PSpice simulation

• 동아시아식생활학회지
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• 제6권3호
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• pp.393-401
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• 1996

This survey was carried out as part of a basic works to improve the extention of native chicken uses. A sample of 282 housewives living in the downtown area of Taegu city were examined using an original questionnaire about their awareness and uses of a native chicken. The results were as follows: The awareness for a chicken dish is significantly different according to the housewives' ages and many respondents evaluated the nutritive value of a native chicken. The housewives preferred chicken boiled plain, spice fried chicken and stewed chicken, in the order. But family members preferred chicken boiled plain, spice fried chicken and french fried chicken, in the order. The frequencies of chicken cooking and buying chicken dishes of the housewives were once permonth and they regarded a native chicken as one of traditional, health and natural foods. They appreciated the taste of a native chicken highly and recognized the price of a native chicken expensive. Also 52.5% of housewives could distinguish a native chicken from the others.

• 한국조리학회지
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• 제5권1호
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• pp.131-148
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• 1999

Cheju's local foods are various but Island being geographically surrounded by water, sea-foods play a greater part in the diet that is quite different from the mainland Most of dishes are prepared from local foods and the marine products. That traditional food that have been developed through the lifestyle are now becoming the great interest to both foreign and domestic guests. In this research, we have concluded that developing a cheju's traditional food manu and local manu cooking method. 1. Improvement of cooking method. - development of cheju's traditional Food material and spice. 2. Use not raw fish - boiling, grilling, frying 3. Improvement of cheju's local Food's name. 4. Use the only Boneless fish. 5. taste reformation of Fermentation Food - Masking the TMA etc. 6. Use the many Spice in local food.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.545-546
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• 2006

The improved model that external capacitances are connected to a conventional BSIM3v3 RF Macro model with Rg and Rsub is developed in this paper. The extracted external capacitances and resistances are modeled by scalable fitting equations. The modeled S-parameters of $0.13{\mu}m$ NMOSFET agree well with measured ones from 10MHz to 10GHz, verifying the accuracy of the improved model.

• 한국전기전자재료학회논문지
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• 제26권1호
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• pp.13-17
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• 2013

In this paper, we designed a charge pump circuit using level shifter for LED driver IC. The designed circuit makes the 15 V output voltage from the 5 V input in condition of 50 kHz switching frequency. The prototype chip which include the proposed charge pump circuit and its several internal sub-blocks such as oscillator, level shifter was fabricated using a 0.35 um 20 V BCD process technology. The size of the fabricated prototype chip is 2,350 um ${\times}$ 2,350 um. We examined performances of the fabricated chip and compared its measured results with SPICE simulation data.

• Transactions on Electrical and Electronic Materials
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• 제12권1호
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• pp.7-10
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• 2011

High voltage (HV) integrated circuits are viable alternatives to discrete circuits in a wide variety of applications. A HV device generally used in these circuits is a lateral double diffused metal oxide semiconductor (LDMOS) transistor. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the poly-silicon and the gate oxide. Several physically based investigations of the bias-dependent drift resistance of HV devices have been conducted, but a complete physical model has not been reported. We propose a new technique to model HV devices using both the BSIM3 SPICE model and a bias dependent resistor model (sub-circuit macro model).

• Journal of information and communication convergence engineering
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• 제19권4호
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• pp.263-268
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• 2021

Although the compact capacitance model of point tunneling types of tunneling field-effect transistors (TFET) has been proposed, those of line tunneling types of TFETs have not been reported. In this study, a compact capacitance model of an L-shaped TFET (LTFET), a line tunneling type of TFET, is proposed using the previously developed surface potentials and current models of P- and L-type LTFETs. The Verilog-A LTFET model for simulation program with integrated circuit emphasis (SPICE) was also developed to verify the validation of the compact LTFET model including the capacitance model. The SPICE simulation results using the Verilog-A LTFET were compared to those obtained using a technology computer-aided-design (TCAD) device simulator. The current-voltage characteristics and capacitance-voltage characteristics of N and P-LTFETs were consistent for all operational bias. The voltage transfer characteristics and transient response of the inverter circuit comprising N and P-LTFETs in series were verified with the TCAD mixed-mode simulation results.

• 정보처리학회논문지D
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• 제9D권5호
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• pp.887-896
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• 2002

SPICE(Software Process Improvement and Capability dEtermination) 평가 모형에 기반한 중소기업형 프로세스 개선 모형으로 SPIRE (Software Process Improvement in Regions of Europe)가 개발되어 제공되고 있다. 그러나 SPIRE에서는 조직의 경영 목적에 맞는 프로세스 선택을 위한 구체적인 지침이나 매핑을 제시하고 있지 못하다. 이 연구에서는 프로세스 선택시 활용할 수 있는 객관적인 경영 목표-프로세스간 매핑 참조 테이블을 작성하고, 이를 활용한 프로세스 선정 방안을 제시한다. 매핑 참조 테이블은 델파이 기법을 활용하여 국내 소프트웨어 프로세스 전문가들의 의견 수렴을 통해 작성되었다. 본 연구에서 제시된 프로세스 선정 기법은 매핑 참조 테이블과 해당 업체 관련자의 주관적인 매핑 정보를 종합적으로 활용하여 최종적으로 개선 대상 프로세스를 선정되도록 한다. 이 연구에서 제시된 선정 방법을 2개의 중소 소프트웨어 조직에 실제 적용하여 활용 가능성을 검토하였다. 매핑 참조 테이블을 사용하여 업체 관련자가 간과하고 있던 주요 프로세스를 평가 대상 프로세스로 선정할 수 있었다.

• 전자공학회논문지C
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• 제36C권10호
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• pp.8-16
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• 1999

본 연구에서는 시뮬레이션 효율을 향상시킨 시뮬레이션 기반의 아날로그 셀 합성기법을 제안한다. 아날로그 셀을 계층적으로 합성하기 위하여 시뮬레이션 기반으로 전류미러, 차동입력단 등 각각의 부회로(sub circuit) 생성기들을 개발하였다. 이 부회로 생성기들을 모듈화 시키고 계층화시킴으로써 OTA(operational transconductance amplifier)나 2단(2-stage) OP-AMP, 비교기(comparator)등 일반적인 아날로그 셀들의 합성을 위하여 사용될 수 있게 하였다. 시뮬레이션 기반의 합성 시간을 줄이기 위하여 2단계 탐색 기법 (2-stage searching scheme)과 시뮬레이션 데이터 재사용기법(simulation data reusing scheme)을 제안하여 적용하였다 아날로그 셀(OTA) 합성 시 301.05sec에서 56.52sec로 최고 81.2%의 합성 시간을 줄이므로 시뮬레이션 기반의 회로 합성시 긴 합성시간의 문제를 해결하였다. 개발한 합성기는 SPICE의 모델 파라미터외에 추가적인 물리적 파라미터들을 필요로 하지 않으며 공정이나 SPICE 모델 레벨(level)에 독립적이기 때문에 새로운 공정에 적용할 때 필요한 준비 시간이 최소화되었다. 본 논문에서는 OTA와 2단 OP-AMP를 각각 합성하여 제안하는 합성기법의 유용성을 입증하였다.