• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.95-100
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• 2006

The GaAs-on-insulator (GOI) wafer fabrication technique has been developed by using ion-cut process, based on hydrogen ion implantation and wafer direct bonding techniques. The hydrogen ion implantation condition for the ion-cut process in GaAs and the associated implantation mechanism have been investigated in this paper. Depth distribution of hydrogen atoms and the corresponding lattice disorder in (100) GaAs wafers produced by 40 keV hydrogen ion implantation were studied by SIMS and RBS/channeling analysis, respectively. In addition, the formation of platelets in the as-implanted GaAs and their microscopic evolution with annealing in the damaged layer was also studied by cross-sectional TEM analysis. The influence of the ion fluence, the implantation temperature and subsequent annealing on blistering and/or flaking was studied, and the optimum conditions for achieving blistering/splitting only after post-implantation annealing were determined. It was found that the new optimum implant temperature window for the GaAs ion-cut lie in $120{\sim}160^{\circ}C$, which is markedly lower than the previously reported window probably due to the inaccuracy in temperature measurement in most of the other implanters.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.3
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• pp.175-180
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• 2003

As the integrated circuit device shrinks to the deep submicron regime, the ion implantation process with high ion dose has been attracted beyond the conventional ion implantation technology. In particular, for the case of boron ion implantation with low energy and high dose, the stabilization and throughput of semiconductor chip manufacturing are decreasing because of trouble due to the machine conditions and beam turning of ion implanter system. In this paper, we focused to the improved characteristics of processing conditions of ion implantation equipment through the modified deceleration mode. Thus, our modified recipe with low energy and high ion dose can be directly apply in the semiconductor manufacturing process without any degradation of stability and throughput.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.946-949
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• 1999

In this research we have developed a reliable, effective and feasible HEI(High-Energy Ion Implantation) process 3D-simulation tool, and then by using it we can predict and analyze the effect of HEI process on characteristics of the standard CMOS device. high-energy ion implantation above 200 keV is inevitable process to form retrograde well and buried layer to prevent leakage current, to conduct field implant for field isolation, and to perform after-gate implantation. The feasible analysis tool is a product of the HEI process modeling verified by comparison of the SIMS experiments with the simulation results. Especially, in this paper, we present the predicting capability of HEI-induced impurity and damage profiles compared with the published SIMS data in order to acquire the reliability of our results ranging from few keV to several MeV for phosphorus and boron implantation.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.7 no.4
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• pp.3-9
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• 2008

The ion implantation technology is generally used in order to improve surface mechanical properties, especially tribological properties, of engineering metals. In this study, experimental works were carried out to investigate the surface properties, such as hardness, wear quantity, wear rate and friction force, of a nitrogen ion implanted tool steel STD11 under dry condition. Specimens for the wear test were made to investigate the influences of the initial ion implantation temperature and the total ion radiation. Wear properties, such as the wear quantity and the wear rate, of the nitrogen ion implanted tool steel were considerably improved, especially under the low sliding speed and the low applied load.

• Journal of Information Display
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• v.8 no.1
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• pp.1-5
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• 2007

We have developed a CMOS LTPS process which requires only five photolithographic masks and only one ion doping step. Drain/Source areas of NMOS TFTs were formed by PECVD deposition of a highly doped precursor layer while PMOS contact areas were defined by ion implantation. Single TFTs, inverters, ring oscillators and shift registers were fabricated. N and p-channel devices reached field effect mobilities of $173cm^2$/Vs and $47cm^2$/Vs, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.178-178
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• 2016

Every display is equipped with a cover glass to protect the underneath displaying devices from mechanical and environmental impact during its use. The strengthened glass such as Gorilla glass.$^{TM}$ has been exclusively adopted as a cover glass in many displays. Conventionally, the strengthened glass has been manufactured via ion-exchange process in wet salt bath at high temperature of around $500^{\circ}C$ for hours of treatment time. During ion-exchange process, Na ions with smaller diameter are substituted with larger-diameter K ions, resulting in high compressive stress in near-surface region and making the treated glass very resistant to scratch or impact during its use. In this study, PIIID (plasma immersion ion implantation and deposition) technique was used to implant metal ions into the glass surface for strengthening. In addition, due to the plasmonic effect of the implanted metal ions, the metal-ion implanted glass samples got colored. To implant metal ions, plasma immersion ion implantation technique combined with HiPIMS method was adopted. The HiPIMS pulse voltage of up to 1.4 kV was applied to the 3" magnetron sputtering targets (Cu, Ag, Au, Al). At the same time, the sample stage with glass samples was synchronously pulse-biased via -50 kV high voltage pulse modulator. The frequency and pulse width of 100 Hz and 15 usec, respectively, were used during metal ion implantation. In addition, nitrogen ions were implanted to study the strengthening effect of gas ion implantation. The mechanical and optical properties of implanted glass samples were investigated using micro-hardness tester and UV-Vis spectrometer. The implanted ion distribution and the chemical states along depth was studied with XPS (X-ray photo-electron spectroscopy). A cross-sectional TEM study was also conducted to investigate the nature of implanted metal ions. The ion-implanted glass samples showed increased hardness of ~1.5 times at short implantation times. However, with increasing the implantation time, the surface hardness was decreased due to the accumulation of implantation damage.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.220-220
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• 1999

In plasma source ion implantation, the target is immersed in the plasma and repetitively biased by negative high voltage pulses to implant the extracted ions from plasma into the surface of the target material. In this way, the problems of line-of-sight implantation in ion-beam ion implantation technique can be effectively solved. In addition, the high dose rate and simplicity of the equipment enable the ion implantation a commercially affordable process. In this work, plasma source ion implantation technique was used to improve the wear resistance of Co-cemented WC. which has been extensively used for high speed tools. Nitrogen and carbon ions were implanted using the pulse bias of -602kV, 25 sec and at various implantation conditions. The implanted samples were examined using scanning Auger electron spectroscopy and XPS to investigate the depth distributions of implanted ions and to reveal the chemical state change due to the ion implantation. The implanted ions were found to have penetrated to the depth of 3000$\AA$. The wear resistance of the implanted samples was measured using pin-on-disc wear tester and the wear tracks were examined with alpha-step profilometer.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.151-151
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• 2012

A new plasma process, i.e., the combination of PIII&D and HIPIMS, was developed to implant non-gaseous ions into materials surface. HIPIMS is a special mode of operation of pulsed-DC magnetron sputtering, in which high pulsed DC power exceeding ~1 kW/$cm^2$ of its peak power density is applied to the magnetron sputtering target while the average power density remains manageable to the cooling capacity of the equipment by using a very small duty ratio of operation. Due to the high peak power density applied to the sputtering target, a large fraction of sputtered atoms is ionized. If the negative high voltage pulse applied to the sample stage in PIII&D system is synchronized with the pulsed plasma of sputtered target material by HIPIMS operation, the implantation of non-gaseous ions can be successfully accomplished. The new process has great advantage that thin film deposition and non-gaseous ion implantation along with in-situ film modification can be achieved in a single plasma chamber. Even broader application areas of PIII&D technology are believed to be envisaged by this newly developed process. In one application of non-gaseous plasma immersion ion implantation, Ge ions were implanted into SiO2 thin film at 60 keV to form Ge quantum dots embedded in SiO2 dielectric material. The crystalline Ge quantum dots were shown to be 5~10 nm in size and well dispersed in SiO2 matrix. In another application, Ag ions were implanted into SS-304 substrate to endow the anti-microbial property of the surface. Yet another bio-application was Mg ion implantation into Ti to improve its osteointegration property for bone implants. Catalyst is another promising application field of nongaseous plasma immersion ion implantation because ion implantation results in atomically dispersed catalytic agents with high surface to volume ratio. Pt ions were implanted into the surface of Al2O3 catalytic supporter and its H2 generation property was measured for DME reforming catalyst. In this talk, a newly developed, non-gaseous plasma immersion ion implantation technique and its applications would be shown and discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.111-111
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• 2007

Further scaling the semiconductor devices down to low dozens of nanometer needs the extremely shallow depth in junction and the intentional counter-doping in the silicon gate. Conventional ion beam ion implantation has some disadvantages and limitations for the future applications. In order to solve them, therefore, plasma source ion implantation technique has been considered as a promising new method for the high throughputs at low energy and the fabrication of the ultra-shallow junctions. In this paper, we study about the effects of DC bias and base pressure as a process parameter. The diluted mixture gas (5% $PH_3/H_2$) was used as a precursor source and chamber is used for vacuum pressure conditions. After ion doping into the Si wafer(100), the samples were annealed via rapid thermal annealing, of which annealed temperature ranges above the $950^{\circ}C$. The junction depth, calculated at dose level of $1{\times}10^{18}/cm^3$, was measured by secondary ion mass spectroscopy(SIMS) and sheet resistance by contact and non-contact mode. Surface morphology of samples was analyzed by scanning electron microscopy. As a result, we could accomplish the process conditions better than in advance.

• Journal of the Korean Vacuum Society
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• v.6 no.4
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• pp.326-336
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• 1997

From the concept that the ion implantation-induced defect is one of the major factors in determining source/drain junction characteristics, high quality ultra-shallow $p^+$-n junctions were formed through the control of ion implantation-induced defects in silicon substrate. In conventional process of the junction formation. $p^+$ source/drain junctions have been formed by $^{49}BF_2^+$ ion implantation followed by the deposition of TEOS(Tetra-Ethyl-Ortho-Silicate) and BPSG(Boro-Phospho-Silicate-Glass) films and subsequent furnace annealing for BPSG reflow. Instead of the conventional process, we proposed a series of new processes for shallow junction formation, which includes the additional low temperature RTA prior to furnace annealing, $^{49}BF_2^+/^{11}B^+$ mixed ion implantation, and the screen oxide removal after ion implantation and subsequent deposition of MTO (Medium Temperature CVD oxide) as an interlayer dielectric. These processes were suggested to enhance the removal of ion implantation-induced defects, resulting in forming high quality shallow junctions.