• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.390-397
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• 2001

A novel self-aligned ESD (Elevated Source Drain) MOSFET structure which can effectively reduce the GIDL (Gate-Induced Drain Leakage) current is proposed and analyzed. The proposed ESD structure is characterized by sidewall spacer and recessed-channel depth which are determined by dry-etching process. Elevation of the Source/Drain extension region is realized so that the low-activation effect caused by low-energy ion implantation can be avoided. Unlike the conventional LDD structures, it is shown that the GIDL current of the ESD structure is suppressed without sacrificing the maximum driving capability. The main reason for the reduction of GIDL current Is the decreased electric field at the point of the maximum band-to-band tunneling as the peak electric field is shifted toward the drain side.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.51-59
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• 1993

A 4${\times}10^{19}cm^{3}$ carbon-doped base AlGaAs/GaAs HBY was grown using carbontetracholoride(CCl$_4$) by atmospheric pressure MOCVD. Abruptness of emitter-base junction was characterized by SIMS(secondary ion mass spectorscopy) and the doping concentration of base layer was confirmed by DXRD(double crystal X-ray diffractometry). Mesa-type HBTs were fabricated using wet etching and lift-off technique. The base sheet resistance of R$_{sheet}$=550${\Omega}$/square was measured using TLM(transmission line model) method. The fabricated transistor achieved a collector-base junction breakdown voltage of BV$_{CBO}$=25V and a critical collector current density of J$_{O}$=40kA/cm$^2$ at V$_{CE}$=2V. The 50$\times$100$\mu$$^2$ emitter transistor showed a common emitter DC current gain of h$_{FE}$=30 at a collector current density of JS1CT=5kA/cm$^2$ and a base current ideality factor of ηS1EBT=1.4. The high frequency characterization of 5$\times$50$\mu$m$^2$ emitter transistor was carried out by on-wafer S-parameter measurement at 0.1~18.1GHz. Current gain cutoff frequency of f$_{T}$=27GHz and maximum oscillation frequency of f$_{max}$=16GHz were obtained from the measured Sparameter and device parameters of small-signal lumped-element equivalent network were extracted using Libra software. The fabricated HBT was proved to be useful to high speed and power spplications.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2518-2520
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• 1998

Silicon can be reactive ion etched (RIE) either isotropically or anisotropically. In this paper, a new micromachining technology combining these two etching characteristics is proposed. In the proposed method, the fabrication steps are as follows. First. a polysilicon layer, which is used as the bottom electrode, is deposited on the silicon wafer and patterned. Then the silicon substrate is etched anisotropically to a few micrometer depth that forms a cavity. Then an PECVD oxide layer is deposited to passivate the cavity side walls. The oxide layers at the top and bottom faces are removed while the passivation layers of the side walls are left. Then the substrate is etched again but in an isotropic etch condition to form a round trench with a larger radius than the anisotropic cavity. Then a sacrificial PECVD oxide layer is deposited and patterned. Then a polysilicon structural layer is deposited and patterned. This polysilicon layer forms a pivot structure of a rocker-arm. Finally, oxide sacrificial layers are etched away. This new micromachining technology is quite simpler than conventional method to fabricate joint structures, and the devices that are fabricated using this technology do not require a flexing structure for motion.

• Journal of the Semiconductor & Display Technology
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• v.4 no.2 s.11
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• pp.39-43
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• 2005

In the study, in order to deposit TaN thin film for diffusion barrier and bottom electrode we made the Plasma Assisted ALD equipment and confirmed the electrical characteristics of TaN thin films grown PAALD method. Plasma Assisted ALD equipment depositing TaN thin film using PEMAT(pentakis(ethylmethlyamino) tantalum) precursor and NH3 reaction gas is shown that TaN thin film deposited high density and amorphous phase with XRD measurement. The degree of diffusion and reaction taking place in Cu/TaN (deposited using 150W PAALD)/$SiO_{2}$/Si systems with increasing annealing temperature was estimated for MOS capacitor property and the $SiO_{2}$, (600${\AA}$)/Si system surface analysis by C-V measurement and secondary ion material spectrometer (SIMS) after Cu/TaN/$SiO_{2}$ (400 ${\AA}$) layer etching. TaN thin film deposited PAALD method diffusion barrier have a good diffusion barrier property up to 500$^{\circ}C$.

• Journal of the Korean Vacuum Society
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• v.19 no.3
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• pp.190-198
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• 2010

Asymmetric model for plasma uniformity by Ar and $CF_4$ was modeled by the antenna structure, the diameter of chamber, and the distance between source and substrate for the development of plasma equipment for 450 mm wafer. The aspect ratio of chamber was divided by diameter, distance from substrate, and pumping port area. And we found the condition with the optimized plasma uniformity by changing the antenna structure. The drift diffusion and quasi-neutrality for simplification were used, and the ion energy function was activated for the surface recombination and etching reaction. The uniformity of plasma density on substrate surface was improved by being far of the distance between substrate wall and chamber wall, and substrate and plasma source. And when the antenna of only 2 turns was used, the plasma uniformity can improve from 20~30% to 4.7%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.4
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• pp.468-480
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• 1993

In this paper, at first, the characteristics of double mode SAW (DMS) resonator are analysed by applying the wave guide model and coupled mode theory to 1-port resonator. The DMS resonators (2-pole), which are arranged in a close, parallel configuration of two identical 1-port resonators on a single plate, and 4-pole DMS filters are designed and fabricated at the center frequency of 150.15 MHz with 3-dB bandwidth of 80 KHz. The empirical design characteristics are obtained from the comparison of experimental and theoretical values resulted from several fabrications, and the narrow bandpass filters are implemented on the basis of the above empirical results, which can be used to mobile communication systems. A ST-cut quartz substrate is selected for the stable temperature-frequence characteristics, and high resolution photolithography is applied to the fabrication of filter to get the fine electrode patterns.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2005.09a
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• pp.35-40
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• 2005

The demand for small and high-capacity optical data storage devices has rapidly increased. The areal density of optical disk is increased using higher numerical aperture objective lens and shorter wavelength source. A wafer-scale stacked micro objective lens with a numerical aperture of 0.85 and a focal length of 0.467mm for the 405nm blue- violet laser was designed and fabricated. A diffractive optical element (DOE) was used to compensate the spherical aberration of the objective lens. Among the various fabrication methods for micro DOE, the UV-replication process is more suitable for mass-production. In this study, an 8-stepped DOE pattern as a master was fabricated by photolithography and reactive ion etching process. A flexible mold was fabricated for improving the releasing properties and shape accuracy in UV-molding process. In the replication process, the effects of exposing time and applied pressure on the replication quality were analyzed. Finally, the shapes of master, mold and molded pattern were measured by optical scanning profiler. The deviation between the master and the molded DOE was less than 0.1um. The efficiency of the molded DOE was measured by DOE efficiency measurement system which consists of laser source, sample holder, aperture and optical power meter, and the measured value was $84.5\%$.

• Korean Journal of Materials Research
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• v.16 no.12
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• pp.731-738
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• 2006

It is seriously considered using Al CMP (chemical mechanical planarization) process for the next generation 45 nm Al wiring process. Al CMP is known that it has a possibility of reducing process time and steps comparing with conventional RIE (reactive ion etching) method. Also, it is more cost effective than Cu CMP and better electrical conductivity than W via process. In this study, we investigated 4 different kinds of slurries based on abrasives for reducing scratches which contributed to make defects in Al CMP. The abrasives used in this experiment were alumina, fumed silica, alkaline colloidal silica, and acidic colloidal silica. Al CMP process was conducted as functions of abrasive contents, $H_3PO_4$ contents and pressures to find out the optimized parameters and conditions. Al removal rates were slowed over 2 wt% of slurry contents in all types of slurries. The removal rates of alumina and fumed silica slurries were increased by phosphoric acid but acidic colloidal slurry was slightly increased at 2 vol% and soon decreased. The excessive addition of phosphoric acid affected the particle size distributions and increased scratches. Polishing pressure increased not only the removal rate but also the surface scratches. Acidic colloidal silica slurry showed the highest removal rate and the lowest roughness values among the 4 different slurry types.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.26 no.10
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• pp.2187-2193
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• 2002

We present a novel method for 3D microfabrication with LIGA process that utilizes a deep X-ray mask in which a micro-actuator is integrated. The integrated micro-actuator oscillates the X-ray absorber, which is formed on the shuttle mass of the micro-actuator, during X-ray exposures to modify the absorbed dose profile in X-ray resist, typically PMMA. 3D PMMA microstructures according to the modulated dose contour are revealed after GG development. An X-ray mask with integrated comb drive actuator is fabricated using deep reactive ion etching, absorber electroplating, and bulk micromachining with silicon-on-insulator (SOI) wafer. 1mm $\times$ 1 mm, 20 $\mu$m thick silicon shuttle mass as a mask blank is supported by four 1 mm long suspension beams and is driven by the comb electrodes. A 10 $\mu$m thick, 50 $\mu$m line and spaced gold absorber pattern is electroplated on the shuttle mass before the release step. The fundamental frequency and amplitude are around 3.6 kHz and 20 $\mu$m, respectively, for a do bias of 100 V and an ac bias of 20 $V_{p-p}$ (peak-peak). Fabricated PMMA microstructure shows 15.4 $\mu$m deep, S-shaped cross section in the case of 1.6 kJ $cm^{-3}$ surface dose and GG development at 35$^{\circ}C$ for 40 minutes.

• Korean Journal of Metals and Materials
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• v.48 no.7
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• pp.667-673
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• 2010

Copper filling into TSV (through-silicon-via) and reduction of the filling time for the three dimensional chip stacking were investigated in this study. A Si wafer with straight vias - $30\;{\mu}m$ in diameter and $60\;{\mu}m$ in depth with $200\;{\mu}m$ pitch - where the vias were drilled by DRIE (Deep Reactive Ion Etching) process, was prepared as a substrate. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to reduce the time required complete the Cu filling into the TSV, the PPR (periodic pulse reverse) wave current was applied to the cathode of a Si chip during electroplating, and the PR (pulse-reverse) wave current was also applied for a comparison. The experimental results showed 100% filling rate into the TSV in one hour was achieved by the PPR electroplating process. At the interface between the Cu filling and Ti/ Au functional layers, no defect, such as a void, was found. Meanwhile, the electroplating by the PR current showed maximum 43% filling ratio into the TSV in an hour. The applied PPR wave form was confirmed to be effective to fill the TSV in a short time.