• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.5
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• pp.18-26
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• 1993

This paper presents the design method for two-dimensional FIR digital filter using optimization scheme. The proposed design method is to extend the optimal one-dimensional filter design algorithm proposed by Parks and McClellan to two-dimensional case. When extending one-dimensional design scheme to two-dimensional one, some problems occur. In this paper we solved the problems by using the least square error model, the two-dimensional Lagrange interpolation, and the modified alternation theory. As a result, the equi-ripple FIR filter is obtained that is more optimal and more specific than the conventional methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.10
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• pp.73-81
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• 2000

This paper presents the design and simulation of a power and area efficient interpolation FIR filter with partitioned look up table (LUT) structure. Using the symmetry of the filters coefficients and the contents of the LUT, the area of the proposed filter is minimized. The two filters share the partitioned LUT and activate the LUT selectively to realize the low power operation. The proposed filter has been designed in a 5.0 Volts 0.6${\mu}m$ CMOS technology. Power consumption results have been obtained from Powermill simulations. Experimental results suggest that the proposed filter reduces both the power consumption by 28% and simultaneously the gate area by 5% simultaneously compared to the previously proposed filters.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.1
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• pp.150-158
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• 2010

Filtering is necessary for the SRC(sample rate converter), that is used to change the sampling rate of a digital signal. The larger the conversion ratio of the sampling rate becomes, the more signal processing is needed for the filter, which means more complexity on realization. Thus it is important to reduce the amount of signal processing for the case of substantial conversion ratios. In this paper it is presented an efficient design method of a multistage FIR(finite impulse response) filter, with which the rate conversion occurs in stages rather than in one step. In this method, filter searching is performed exhaustively over all possible factorization of the conversion ratio, and also the filter complexity is measured based on direct realization rather than on estimation. It has been shown a designed multistage filter to have a less number of multiplications for filtering operation in comparison with a conventionally designed one. It has also been found that by allowing some variations of the filter architecture such as a halfband filter or a filter with multiple transition bands, the number of multiplications can be reduced further.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.152-160
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• 1994

Two dimensional interpolation filter for HD-MAC is designed with 1.0 .mu.m CMOS standard cells and verified by logic simulation. The interpolator uses FMH(FIR-Median Hybrid) filter. The median filter, which is the most complicated part of FMH filtre, is simply implemented by modifying Hadian-Sobel algorithm. the filter generates accurately the missed pixel data of luminance and chrominance with the worst case simulation condition at 27MHz clock rates.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.11-21
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• 1999

This paper has been proposed a structure composed of FIRs and IIR filters as digital interpolation filter to integrate the off-chip analog low-pass filter of audio DAC. The passband ripple (>$0.41{\times}fs$), passband attenuation(>at$0.41{\times}fs$) and stopband attenuation(<$0.59{\times}fs$) of the ${\Delta}{\Sigma}$ modulator output using the proposed digital interpolation filter had ${\pm}0.001[dB]$, -0.0025[dB] and -75[dB], respectively. Also the inband group delay was 30.07/fs[s] and the error of group delay was 0.1672%. Also, the attenuation of stopband has been increased -20[dB] approximately at 65[kHz], out-of-band. Therefore the RC products of analog low-pass filter on chip have been decreased compared with the conventional digital interpolation filter structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6A
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• pp.464-472
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• 2012

In this paper, we propose a new super-resolution algorithm that uses successive frames by applying the block matching motion estimation algorithm. Usually, single frame super-resolution algorithms are based on probability or discrete wavelet transform (DWT) approach to extract high-frequency components of the input image, but only limited information is available for these algorithms. To solve this problem, various multiple-frame based super-resolution algorithms are proposed. The accuracy of registration between frames is a very important factor for the good performance of an algorithm. We therefore propose an algorithm using 6-Tap FIR filter to increase the accuracy of the image registration with sub-pixel unit. Proposed algorithm shows better performance than other conventional interpolation based algorithms such as nearest neighborhood, bi-linear and bi-cubic methods and results in about the same image quality as DWT based super-resolution algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.109-116
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• 2014

This paper presents a high-efficiency digital class-D audio amplifier using a composite interpolation filter for portable audio devices. The proposed audio amplifier is composed of an interpolation filter, a delta-sigma modulator, and a class-D output stage. To reduce power consumption, the designed interpolation filter has an optimized composite structure that uses a direct-form symmetric and Lagrange FIR filters. Compared to the filters with homogeneous structures, the hardware cost and complexity are reduced by about half by the optimization. The coefficients of the digital delta-sigma modulator are also optimized for low power consumption. The class-D output stage has gate driver circuits to reduce shoot-through current. The implemented class-D audio amplifier exhibited a high efficiency of 87.8 % with an output power of 57 mW at a load impedance of $16{\Omega}$ and a power supply voltage of 1.8 V. An outstanding signal-to-noise ratio of 90 dB and a total harmonic distortion plus noise of 0.03 % are achieved for a single-tone input signal with a frequency of 1 kHz.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.12 no.4
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• pp.71-79
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• 1992

In general, the accelerogram of earthquake ground motion or the accelerogram obtained from dynamic tests contain various errors. In these errors of the accelerograms, there are instrumental errors(magnitude and phase distortion) due to the response characteristics of accelerometer and the digitizing error concentrated in low and high frequency components and random errors. Then, these errors may be detrimental to the results of data processing and dynamic analysis. An efficient method which can correct the errors of the accelerogram is proposed in this study. The correction of errors can be accomplished through four steps as followes ; 1) using an interpolation method a data form appropriate to the error correction is prepared, 2) low and high frequency errors of the accelerogram are removed by band-pass filter between prescribed frequency limits, 3) instrumental errors are corrected using dynamic equilibrium equation of the accelerometer, 4) velocity and displacement are obtained by integrating corrected accelerogram. Presently, infinite impulse response(IIR) filter and finite impulse response (FIR) filter are generally used as band-pass filter. In the proposed error correction procedure, the deficiencies of FIR filter and IIR filter are reduced and, using the properties of the differentiation and the integration of Fourier transform, the accuracy of instrument correction and integration is improved.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.7C
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• pp.713-724
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• 2006

The purpose of this study is to design, implement and verify the pre-modulation filter with the variable -3dB cutoff frequency and linear phase response for bandlimiting the allocation of radio frequency bandwidth for PCM/FM transmission. For the design of this required filter, the digital FIR filter, DAC system and tuneable 2nd order LPF have been constructed and simulated according to the attenuation characteristic requirement of the amplitude frequency response by each stage. From these results, we have implemented the filter and verified the analog conversion hardware part which is composed of DAC system and tuneable 2nd order LPF for the interpolation of the discrete sequences. Especially this paper proposes and carries out the verification processes using the tone generator and the calibration procedures for more precise frequency response of the filter.

• Journal of Satellite, Information and Communications
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• v.5 no.1
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• pp.32-37
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• 2010

The algorithm of multiple channel signal processing requires the flexibility of variable frequency band, efficient allocation of transmission power, and flexible frequency band reallocation to satisfy various service types which requires different transmission rates and frequency band. There are three methods including per-channel approach, multiple tree approach, and block approach performing frequency band reallocation method by channelization and dechannelization in the multiple-channel signal. This paper proposes an improved per-channel approach for converting the frequency band of multiple carrier signals efficiently. The proposed algorithm performs decimation and interpolation using CIC(cascaded integrator comb filter), half-band filter, and FIR filter. In addition, it performs filtering of each sub-channel, and reallocates channel band through FIR low-pass filter in the multiple-channel signal. The computer simulation result shows that the perfect reconstruction of output signal and the flexible frequency band reallocation is performed efficiently by the proposed algorithm.