• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.2
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• pp.96-105
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• 2021

Large-scale power converters consist of series or parallel module combinations. In these modular converter systems, the interleaving technique can be applied to improve capacitor reliability by reducing the ripple of the I/O current in which each module operates as a phase difference. However, when applying the interleaving technique for conventional three-level boost converters, the short-circuit period of the converter can be an obstacle. Such problem is caused by the absence of a low-level inductor of the conventional three-level boost converter. To solve this problem, a three-level boost converter with a low-level inductor is proposed and analyzed to enable interleaved operation. In the proposed circuit, the current ripple of the output capacitor depends on the neutral point connections between the modules. In this study, the ripple current is analyzed by the neutral point connections of the three-level boost converter that has a low-level inductor, and the effectiveness of the proposed circuit is proven by simulation and experiment.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.11a
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• pp.237-240
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• 2004

For the paralleled operation of DC/DC converters, the current sharing between each modules is the most important for the reliability of the power system. Interleaving method is commonly used with many paralleling schemes for the reduction of the ripple in the output voltage of paralleled converters and there are many commercial IC for interleaving application appliable. But for all of them, it is impossible to detect the number of module in operating and then change the phase of them automatically. In this paper, a novel paralleling method is proposed for the converter parallel operation, which detects the number of modules in active and sets the phases of PWM signals applied to each modules autonomously. This can greatly improve the output voltage ripple and reliability of the system. The expandibility of modular number can be done very easily by just adding several parts.

• Journal of IKEEE
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• v.24 no.2
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• pp.586-591
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• 2020

An interleaved current-fed high step-up DC-DC converter is proposed. Besides high voltage gain, a low ripple input current is achieved by adopting interleaving operation. Moreover, soft-switching characteristic of the proposed converter reduces switching losses of active power switches and raise the conversion efficiency. The reverse-recovery problem of output rectifiers is also alleviated by controlling the current changing rates of diodes by utilizing the leakage inductances of transformers. Experimental results obtained on a 200W prototype are discussed.

• Journal of Electrical Engineering and Technology
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• v.4 no.3
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• pp.405-409
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• 2009

A polarization-independent multiwavelength-switchable fiber filter is proposed based on a polarization beam splitter and fiber coupler, which can function as a polarization-independent transmission or reflection-type interleaving filter. The proposed filter consists of a polarization beam splitter and a Sagnac birefringence loop composed of a 50:50 coupler, high birefringent fibers, and two quarter-wave plates. In the proposed filter, a transmission-type interleaver with a channel isolation > 18 dB or a reflection-type one with a channel isolation of ${\sim}3$ dB, whose channel spacing and switching displacement were 0.8 and 0.4 nm in common, respectively, could be obtained. A channel interleaving operation could be performed by the proper control of waveplates within the Sagnac birefringence loop.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.330-331
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• 2011

The interleaving method is usually used to reduce the ripple of output current of filter inductor in parallel operation of PWM DC/DC converter. Although the current ripple of filter inductor decreases, each current ripple of filter inductor is not decreased. In this study, the operation of interleaved buck converter with coupled inductor is analyzed in each operation mode. It is verified through experiment. The possibility of application to grid connected inverter with parallel operation is identified.

• Journal of IKEEE
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• v.19 no.2
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• pp.168-175
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• 2015

In this paper, we propose FPGA design technique for rotating LED display device which is capable of displaying videos with the use of the afterimage effect. The proposed technique is made up of image data correction process based on inverse gamma correction and error diffusion, block interleaving process, and data serial output process. The data correction process based on inverse gamma correction and error diffusion is an image data correction step in which image data received are corrected by inverse gamma correction process to convert the data into linear brightness characteristics, and by error diffusion process to reduce the brightness reduction phenomenon in low-gray-level which is caused by inverse gamma correction. In the block interleaving process, the data of the frames entered transversely are first saved in accordance with entrance order, and then only the longitudinal image data are read. The data serial output process is applied to convert the parallel data in a rotating location into serial data and send them to LED Driver IC, in order to send data which will be displayed on high-speedy rotating LED Bar. To evaluate the accuracy of the proposed FPGA design technique, this paper used XC6SLX45-FG484, a Spartan 6 family of Xilinx, as FPGA, and ISE 14.5 as a design tool. According to the evaluation analysis, it was found that goal values were consistent with simulation values in terms of accurate operation of inverse gamma and error diffusion correction, block interleaving operation, and serialized operation of image data.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.10
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• pp.7-13
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• 2009

By incorporating a polarization beam splitter and fiber coupler, we propose a fiber-optic multiwavelength-switchable interleaving filter that can function as a polarizaiton-independent transmission or reflection-type one. The proposed filter consists of a polarizaiton beam splitter and a Sagnac birefringence loop that is composed of a 50:50 coupler, polarizaiton-maintaining fibers, and two quarter-wave plates. In the proposed filter, a transmission-type filter with a channel isolation > 18[dB] or a reflection-type one with a channel isolation ~3[dB], whose channel spacing and switching displacement were 0.8 and 0.4[nm] in common, respectively, could be obtained. Channel interleaving operation could be performed by the proper control of waveplates within the Sagnac birefringence loop.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.447-448
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• 2020

3-Level Boost Converter(TLB)의 병렬 연결 시, 배터리 및 커패시터의 맥동 전류 저감을 위하여 인터리빙 동작이 요구된다. 그러나 기존의 TLB 병렬모듈은 인터리빙 운전이 불가능하다. 본 논문에서는 TLB 병렬모듈의 인터리빙 운전이 가능한 회로의 동작을 기술하고, 커패시터 중성점 연결 시 맥동 전류저감 효과를 분석한다.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.49 no.7
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• pp.581-588
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• 2021

This paper deals with a beam scheduling method in fighter interleaving mode. Not only the priority of tasks but also operational requirements that air-to-ground and air-to-air search tasks should be executed alternatively are established to maximize high-quality of situational awareness. We propose a real-time heuristic beam scheduling method that is advanced from WMDD to satisfies the requirements. The proposed scheduling method is implemented in a simulation environment resembling the task processing mechanism and measurement model of a radar. Performance improvement in terms of task delay time is observed.

• The KIPS Transactions:PartA
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• v.18A no.4
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• pp.135-142
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• 2011

This research is to design an effective buffer structure and its management for flash memory based high performance SSDs (Solid State Disks). Specifically conventional SSDs tend to show asymmetrical performance in read and /write operations, in addition to a limited number of erase operations. To minimize the number of erase operations and write latency, the degree of interleaving levels over multiple flash memory chips should be maximized. Thus, to increase the interleaving effect, an effective buffer structure is proposed for the SSD with a hybrid address mapping scheme and super-block management. The proposed buffer operation is designed to provide performance improvement and enhanced flash memory life cycle. Also its management is based on a new selection scheme to determine random and sequential accesses, depending on execution characteristics, and a method to enhance the size of sequential access unit by aggressive merging. Experiments show that a newly developed mapping table under the MBA is more efficient than the basic simple management in terms of maintenance and performance. The overall performance is increased by around 35% in comparison with the basic simple management.