• Proceedings of the Korean Institute of Surface Engineering Conference
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• 1998.11a
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• pp.27-28
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• 1998

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.1121-1124
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• 2001

In this study, we verify th effects of pattern density on interlayer dielectric chemical mechanical polishing process based on the analysis of Preston's equation and confirm this analysis by several experiments. Appropriate modeling equation, transformed form Preston's equations used in glass polishing, will be suggested and described the effects of this modeling during pattern wafer ILD CMP. Results indicate that the modeling is well agreed to middle density structure of the die in pattern wafer, but has some error in low and high density structure of the die. Actually, the die used in Fab, was designed to have a appropriate density, therefore this modeling will be suitable for estimating the results of ILD CMP.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.935-938
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• 1997

Recently, the minimum line width shows a tendency to decrease and the multi-level increase in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. But there are several defects in CMP such as micro-scratches, abrasive contaminations, and non-uniformity of polished wafer edges. Wet etching include of Spin-etching can improve he defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(INterlayer-Dielectric) was removed by CMP and wet-etching methods in order to investigate the superiority of wet etching mechanism. In the thin film wafer, the results were evaluated at a viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And pattern step height was also compared for planarization characteristics of the patterned wafer.

• Transactions on Electrical and Electronic Materials
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• v.8 no.2
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• pp.53-57
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• 2007

In this study, a novel slurry containing ceria as the abrasive particles was analyzed in terms of its frictional, thermal and kinetic attributes for interlayer dielectric (ILD) CMP application. The novel slurry was used to polish 200-mm blanket ILD wafers on an $IC1000_{TM}$ K-groove pad with in-situ conditioning. Polishing pressures ranged from 1 to 5 PSI and the sliding velocity ranged from 0.5 to 1.5 m/s. Shear force and pad temperature were measured in real time during the polishing process. The frictional analysis indicated that boundary lubrication was the dominant tribological mechanism. The measured average pad leading edge temperature increased from 26.4 to $38.4\;^{\circ}C$ with the increase in polishing power. The ILD removal rate also increased with the polishing power, ranging from 400 to 4000 A/min. The ILD removal rate deviated from Prestonian behavior at the highest $p{\times}V$ polishing condition and exhibited a strong correlation with the measured average pad leading edge temperature. A modified two-step Langmuir-Hinshelwood kinetic model was used to simulate the ILD removal rate. In this model, transient flash heating temperature is assumed to dominate the chemical reaction temperature. The model successfully captured the variable removal rate behavior at the highest $p{\times}V$ polishing condition and indicates that the polishing process was mechanical limited in the low $p{\times}V$ polishing region and became chemically and mechanically balanced with increasing polishing power.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.86-89
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• 2003

Chemical Mechanical Planarization(CMP) has been accepted as the most effective processes for ultra large scale integrated (ULSI) chip manufacturing. However, as the polishing process continues, pad pores get to be glazed by polishing residues, which hinder the supply of new slurry. And pad surface is ununiformly deformed as real contact distance. These defects make material removal rate(MRR) decrease with a number of polishied wafer. Also the desired within-chip planarity, within wafer non-uniformity(WIWNU) and wafer to wafer non-uniformity(WTWNU) arc unable to be achieved. So, pad conditioning in CMP Process is essential to overcome these defects. The eletroplated or brazed diamond conditioner is used as the conventional conditioning. And. allumina long fiber, the jet power of high pressure deionized water, vacuum compression. ultrasonic conditioner aided by cavitation effect and ceramic plate conditioner are once used or under investigation. But. these methods arc not sufficient for ununiformly deformed pad surface and the limits of conditioning effect. So this paper focuses on the characteristics of diamond conditioner which reopens glazed pores and removes ununiformly deformed pad away.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.651-652
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• 2005

Chemical mechanical polishing (CMP) has emerged as the planarization technique of choice in integrated circuit manufacturing. Especially, polishing pad is considered as one of the most important consumables because of its properties. Generally, conventional polishing pad has irregular pores and asperities. If conditioning process is except from whole polishing process, smoothing of asperities and pore glazing occur on the surface of the pad, so repeatability of polishing performances cannot be expected. In this paper, CMP pad with microstructure was made using micro-molding technology and repeatability of ILD(interlayer dielectric) CMP performances and was evaluated.

• Journal of the Semiconductor & Display Technology
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• v.7 no.1
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• pp.41-45
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• 2008

We studied the electrical characteristics of low-k SiOCR interlayer dielectric(ILD) films fabricated by plasma enhanced chemical vapor deposition (PECVD). The precursor bis-trimethylsilylmethane (BTMSM) was introduced into the reaction chamber with the various flow rates. The absorption intensities of Si-O-$CH_x$, bonding group and Si-$CH_x$, bonding group changed synchronously for the variation of precursor flow rate, but the intensity of Si-O-Si(C) responded asynchronously with the $CH_x$, combined bonds. The SiOCH films revealed ultra low dielectric constant around 2.1(1) and reduced further below 2.0 by heat treatments.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.1
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• pp.47-52
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• 2009

We studied the electrical characteristics of low-k SiOCH interlayer dielectric(ILD) films fabricated by plasma enhanced chemical vapor deposition (PECVD). BTMSM precursor was evaporated and introduced with the flow rates from 16 sccm to 25 sccm by 1 sccm step with the constant flow rate of 60 sccm $O_2$ in process chamber. The vibrational groups of SiOCH thin films were analyzed by FT!IR absorption lines, and the dielectric constant of the low-k SiOCH thin films were obtained by measuring C-V characteristic curves. The heat treatment on SiOCH thin films reduced the FTIR absorption intensity of the Si-O-$CH_3$ bonding group and Si-$CH_3$ bonding group but increased the intensity of Si-O-Si(C) bonding group. The SiOCH ILD films could have low dielectric constant $k\;{\simeq}\;2$ and also be reduced further by decreasing the $CH_3$ group density and increasing Si-O-Si(C) group density through annealing process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.4
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• pp.362-367
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• 2008

We have Manufactured the low-k dielectric interlayer fabricated by plasma enhanced chemical vapor deposition (PECVD), The thin film of SiOCH is studied correlation between components and Dielectric constant. The precursor was evaporated and introduced with the flow rates from 16 sccm to 25 sccm by 1sccm step in the constant flow rate of 60 sccm $O_2$ in process chamber. The chemical characteristics of SiOCH were analyzed by measuring FT/IR absorption lines and obtained each dielectric constant measuring C-V. Then compare respectively. ILD of BTMSM/$O_2$ could have low dielectric constant about $k\sim2$, and react sensitively. Also dielectric constant could be decreased by the effects of decreasing $CH_3$ and growing Si-O-Si(C) after annealing process.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.5
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• pp.149-158
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• 2002

Recently, the minimum line width shows a tendency to decrease and the multi-level increases in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. However there are several defects in CMF, such as micro-scratches, abrasive contaminations and non-uniformity of polished wafer edges. Wet etching process including spin-etching can eliminate the defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(Interlayer-Dielectric) was removed by CMP and wet etching process using DHF(Diluted HF) in order to investigate the possibility of planrization by wet etching mechanism. In the thin film wafer, the results were evaluated from the viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And the pattern step heights were also compared for the purpose of planarity characterization of the patterned wafer. Moreover, Chemical polishing process which is the wet etching process with mechanical energy was introduced and evaluated for examining the characteristics of planarization.