• Title/Summary/Keyword: Interlayer Dielectric

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Microstructure and Ferroelectric Properties of PZT Thin Films Deposited on various Interlayers by R.F. Magnetron Sputtering (R.F. Magnetron Sputtering으로 다양한 Interlayer 층위에 형성시킨 PZT 박막의 미세구조와 강유전 특성)

  • Park, Chul-Ho;Choi, Duck-Young;Son, Young-Guk
    • Journal of the Korean Ceramic Society
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    • v.39 no.8
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    • pp.742-749
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    • 2002
  • The PZT thin films werre deposited on Pt/Ti/$SiO_2$/Si substrate by R. F. magnetron sputtering with $Pb_{1.1}Zr_{0.53}Ti_{0.47}O_3$ target. When interlayers(PbO, $TiO_2$, PbO/$TiO_2$) were inserted between PZT and Pt, the crystallization of the PZT thin films was considerably improved and the processing temperature was lowered. Compared to the pure PZT thin films, dielectric constant, dielectric loss and polarization properties of PZT thin films with interlayers were considerably improved. From XPS depth profile analysis, it was confirmed that PZT thin films and interlayers existed independently. In particular, PZT thin films deposited on interlayer(PbO/$TiO_2$) showed the best dielectric property (${\varepsilon}_r$=414.94, tan${\delta}$=0.0241, Pr=22${\mu}C/cm^2$).

Characterization of low-k dielectric SiOCH film deposited by PECVD for interlayer dielectric (PEDCVD로 증착된 ILD용 저유전 상수 SiOCH 필름의 특성)

  • Choi, Yong-Ho;Kim, Jee-Gyun;Lee, Heon-Yong
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.11a
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    • pp.144-147
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    • 2003
  • Cu+ ions drift diffusion in formal oxide film and SiOCH film for interlayer dielectric is evaluated. The diffusion is investigated by measuring shift in the flatband voltage of capacitance/voltage measurements on Cu gate capacitors after bias temperature stressing. At a field of 0.2MV/cm and temperature $200^{\circ}C,\;300^{\circ}C,\;400^{\circ}C,\;500^{\circ}C$ for 10min, 30min, 60min. The Cu+ ions drift rate of $SiOCH(k=2.85{\pm}0.03)$ film is considerable lower than termal oxide. As a result of the experiment, SiOCH film is higher than Thermal oxide film for Cu+ drift diffusion resistance. The important conclusion is that SiOCH film will solve a causing reliability problems aganist Cu+ drift diffuion in dielectric materials.

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Properties of Interlayer Low Dielectric Polyimide during Aluminum Etching with Electron Cyclotron Resonance Etcher System

  • Kim, Sang-Hoon;Ahn, Jin-Ho
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2000.04a
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    • pp.87-96
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    • 2000
  • The properties of polyimide for interlayer dielectric applications are investigated during plasma etching of aluminum on it. Chlorine-based plasma generally used for aluminum etching results in an increase in the (dielectric constant of polyimide, while $SF_6$ plasma exhibits a high polyimide etch rate and a reducing effect of the dielectric constant. The leakage current of polyimide is significantly suppressed after plasma exposure. An optimal combination of Al etch with $Cl_6$ plasma and polyimide etch with $SF_6$ plasma is expected to be a good tool for realizing multilevel metallization structures.

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3.5 inch QCIF AMOLED Panel with Ultra Low Temperature Polycrystalline Silicon Thin Film Transistor on Plastic Substrate

  • Kim, Yong-Hae;Chung, Choong-Heui;Moon, Jae-Hyun;Park, Dong-Jin;Lee, Su-Jae;Kim, Gi-Heon;Song, Yoon-Ho
    • 한국정보디스플레이학회:학술대회논문집
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    • 2007.08a
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    • pp.717-720
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    • 2007
  • We fabricated the 3.5 inch QCIF AMOLED panel with ultra low temperature polycrystalline silicon TFT on the plastic substrate. To reduce the leakage current, we used the triple layered gate metal structure. To reduce the stress from inorganic dielectric layer, we applied the organic interlayer dielectric and the photoactive insulating layer. By using the interlayer dielectric as a capacitor, the mask steps are reduced up to five.

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A Global Planarization of Interlayer Dielectric Using Chemical Mechanical Polishing for ULSI Chip Fabrication (화학기계적폴리싱(CMP)에 의한 층간절연막의 광역평탄화에 관한 연구)

  • Jeong, Hea-do
    • Journal of the Korean Society for Precision Engineering
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    • v.13 no.11
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    • pp.46-56
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    • 1996
  • Planarization technique is rapidly recognized as a critical step in chip fabrication due to the increase in wiring density and the trend towards a three dimensional structure. Global planarity requires the preferential removal of the projecting features. Also, the several materials i.e. Si semiconductor, oxide dielectric and sluminum interconnect on the chip, should be removed simultaneously in order to produce a planar surface. This research has investihgated the development of the chemical mechanical polishing(CMP) machine with uniform pressure and velocity mechanism, and the pad insensitive to pattern topography named hard grooved(HG) pad for global planarization. Finally, a successful result of uniformity less than 5% standard deviation in residual oxide film and planarity less than 15nm in residual step height of 4 inch device wafer, is achieved.

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Si-to-Si Electrostatic Bonding using LSG Film as an Interlayer (LSG Interlayer를 이용한 실리콘-실리콘 정전 열 접합)

  • Ju, Byeong-Gwon;Jeong, Ji-Won;Lee, Deok-Jung;Lee, Yun-Hui;Choe, Du-Jin;O, Myeong-Hwan
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.48 no.9
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    • pp.672-675
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    • 1999
  • Si-to-Si electrostatic bonding was carried out by employing LSG interlayer instead of conventional Corning #7740 interlayer in order to improve bonding properties. The surface roughness and dielectric breakdown field of the LSG interlayers deposited on Si substrates were investigated. Also, the bonding interface, bonding strength and bonding mechanism were discussed for the electrostatically-bonded Si-Si wafer pairs having LSG interlayers.

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Effect of gas composition on the characteristics of a-C:F thin films for use as low dielectric constant ILD (가스 조성이 저유전상수 a-C:F 층간절연막의 특성에 미치는 영향)

  • 박정원;양성훈;이석형;손세일;오경희;박종완
    • Journal of the Korean Vacuum Society
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    • v.7 no.4
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    • pp.368-373
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    • 1998
  • As device dimensions approach submicrometer size in ULSI, the demand for interlayer dielectric materials with very low dielectric constant is increased to solve problems of RC delay caused by increase in parasitic resistance and capacitance in multilevel interconnectins. Fluorinated amorphous carbon in one of the promising materials in ULSI for the interlayer dielectric films with low dielectric constant. However, poor thermal stability and adhesion with Si substrates have inhibited its use. Recently, amorphous hydrogenated carbon (a-C:H) film as a buffer layer between the Si substrate and a-C:F has been introduced because it improves the adhesion with Si substrate. In this study, therfore, a-C:F/a-C:H films were deposited on p-type Si(100) by ECRCVD from $C_2F_6, CH_4$and $H_2$gas source and investigated the effect of forward power and composition on the thickness, chemical bonding state, dielectric constant, surface morphology and roughness of a-C:F films as an interlayer dielectric for ULSI. SEM, FT-IR, XPS, C-V meter and AFM were used for determination of each properties. The dielectric constant in the a-C:F/a-C:H films were found to decrease with increasing fluorine content. However, the dielectric constant increased after furnace annealing in $N_2$atomosphere at $400^{\circ}C$ for 1hour due to decreasing of flurorine content. However, the dielectric constant increased after furnace annealing in $N_2$atmosphere at $400^{\circ}C$ for 1hour due to decreasing of fluorine concentration.

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용액공정을 이용한 SiOC/SiO2 박막제조

  • Kim, Yeong-Hui;Kim, Su-Ryong;Gwon, U-Taek;Lee, Jeong-Hyeon;Yu, Yong-Hyeon;Kim, Hyeong-Sun
    • Proceedings of the Materials Research Society of Korea Conference
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    • 2009.11a
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    • pp.36.2-36.2
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    • 2009
  • Low dielectric materials have been great attention in the semiconductor industry to develop high performance interlayer dielectrics with low k for Cu interconnect technology. In our study, the dielectric properties of SiOC /SiO2 thin film derived from polyphenylcarbosilane were investigated as a potential interlayer dielectrics for Cu interconnect technology. Polyphenylcarbosilane was synthesized from thermal rearrangement of polymethylphenylsilane around $350^{\circ}C{\sim}430^{\circ}C$. Characterization of synthesized polyphenylcarbosilane was performed with 29Si, 13C, 1H NMR, FT-IR, TG, XRD, GPC and GC analysis. From FT-IR data, the band at 1035 cm-1 is very strong and assigned to CH2 bending vibration in Si-CH2-Si group, indicating the formation of the polyphenylcarbosilane. Number average of molecular weight (Mn) of the polyphenylcarbosilane synthesized at $400^{\circ}C$ for 6hwas 2, 500 and is easily soluble in organic solvent. SiOC/SiO2 thin film was fabricated on ton-type silicon wafer by spin coating using 30wt % polyphenylcarbosilane incyclohexane. Curing of the film was performed in the air up to $400^{\circ}C$ for 2h. The thickness of the film is ranged from $1{\mu}m$ to $1.7{\mu}m$. The dielectric constant was determined from the capacitance data obtained from metal/polyphenylcarbosilane/conductive Si MIM capacitors and show a dielectric constant as low as 2.5 without added porosity. The SiOC /SiO2 thin film derived from polyphenylcarbosilane shows promising application as an interlayer dielectrics for Cu interconnect technology.

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Effect of the Cl-based Plasma for Al Etching on the Interlayer Low Dielectric Polyimide (염소 플라즈마를 이용한 알루미늄 식각 공정이 저유전상수 층간절연막 polyimide에 미치는 영향)

  • 문호성;김상훈;이홍구;우상균;김경석;안진호
    • Journal of the Microelectronics and Packaging Society
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    • v.6 no.1
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    • pp.75-79
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    • 1999
  • We have studied electrical properties of polyimide for the next generation interlayer low dielectric during plasma etching. Dielectric constant of polyimide exposed to Cl-based plasma, which is used in aluminum etching, increased, while that of polyimide exposed to $SF_{6}$ plasma decreased. The results are related to fluorine or chlorine bonds as examined by FTIR ana XPS analyses. So, we expect that Cl-based 1)miasma etching of aluminum followed by $SF_{6}$ plasma exposure results in the prevention of post-etch corrosion and decrease of dielectric constant.

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