• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.180-180
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• 2010

Thin film transistors (TFTs) based on oxide semiconductors have emerged as a promising technology, particularly for active-matrix TFT-based backplanes. Currently, an amorphous oxide semiconductor, such as InGaZnO, has been adopted as the channel layer due to its higher electron mobility. However, accurate and repeatable control of this complex material in mass production is not easy. Therefore, simpler polycrystalline materials, such as ZnO and $SnO_2$, remain possible candidates as the channel layer. Inparticular, ZnO-based TFTs have attracted considerable attention, because of their superior properties that include wide bandgap (3.37eV), transparency, and high field effect mobility when compared with conventional amorphous silicon and polycrystalline silicon TFTs. There are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems, the stability of ZnO-based TFTs, is as yet unsolved since ZnO-based TFTs usually contain defects in the ZnO channel layer and deep level defects in the channel/dielectric interface that cause problems in device operation. The quality of the interface between the channel and dielectric plays a crucial role in transistor performance, and several insulators have been reported that reduce the number of defects in the channel and the interfacial charge trap defects. Additionally, ZnO TFTs using a high quality interface fabricated by a two step atomic layer deposition (ALD) process showed improvement in device performance In this study, we report the fabrication of high performance ZnO TFTs with a $Si_3N_4$ gate insulator treated using plasma. The interface treatment using electron cyclotron resonance (ECR) $O_2$ plasma improves the interface quality by lowering the interface trap density. This process can be easily adapted for industrial applications because the device structure and fabrication process in this paper are compatible with those of a-Si TFTs.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.380-380
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• 2010

Currently, organic light-emitting diodes (OLEDs) have been proven of their readiness for commercialization in terms of lifetime and efficiency. In accordance with emerging new technologies, enhancement of light efficiency and extension of application fields are required. Particularly inverted structures, in which electron injection occurs at bottom and hole injection on top, show crucial advantages due to their easy integration with Si-based driving circuits for active matrix OLED as well as large open area for brighter illumination. In order to get better performance and process reliability, usually a proper buffer layer for carrier injection is needed. In inverted top emission OLED, the buffer layer should protect underlying organic materials against destructive particles during the electrode deposition, in addition to increasing their efficiency by reducing carrier injection barrier. For hole injection layers, there are several requirements for the buffer layer, such as high transparency, high work function, and reasonable electrical conductivity. As a buffer material, a few kinds of transition metal oxides for inverted OLED applications have been successfully utilized aiming at efficient hole injection properties. Among them, we chose 2 nm of $WO_3$ between NPB [N,N'-bis(1-naphthyl)-N,N'-diphenyl-1,1'-biphenyl-4,4'-diamine] and Au (or Al) films. The interfacial energy-level alignment and chemical reaction as a function of film coverage have been measured by using in-situ ultraviolet and X-ray photoelectron spectroscopy. It turned out that the $WO_3$ interlayer substantially reduces the hole injection barrier irrespective of the kind of electrode metals. It also avoids direct chemical interaction between NPB and metal atoms. This observation clearly validates the use of $WO_3$ interlayer as hole injection for inverted OLED applications.

• 대한금속재료학회지
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• 제48권12호
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• pp.1116-1122
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• 2010

Metal interconnections of multilayer Al/Ni and TiW/seed-Ni/Ni were formed on glass, and the adhesion strength and nanoindentation response of the composite layers were evaluated. The Al/Ni multilayer was formed by an anodic bonding of glass to Al and subsequent electroless plating of Ni, while the TiW/Ni multilayer was fabricated by sputter deposition of TiW and seed-Ni onto glass and electroless plating of Ni. Because of the diffusion of aluminum into glass during the anodic bonding, anodically bonded glass/Al joint exhibited greater interfacial strength than the sputtered glass/TiW one. The Al/Ni on glass also showed excellent resistance against delamination by bending deformation compared to the TiW/seed-Ni/Ni on glass. From the nanoindentation experiment of each metal layer on glass, it was found that the aluminum layer had extremely low hardness and elastic modulus similar to the glass substrate and played a beneficial role in the delamination resistance by lessening stress intensification at the joint. The indentation data of the multilayers also supported superior joint reliability of the Al/Ni to glass compared to that of the TiW/seed-Ni/Ni to glass.

• Composites Research
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• 제36권5호
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• pp.342-348
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• 2023

최근 웨어러블 소자를 이용한 신체와 주변 온도의 실시간 모니터링에 대한 수요가 급격히 증가하고 있다. 그래핀 기반 써미스터가 고성능 유연 온도 센서로 개발되어 왔다. 본 연구에서는 단일층 그래핀의 온도 측정 성능을 개선하기 위하여 표면에 polyethylenimine(PEI)를 코팅하여 저항 온도 계수(TCR)를 조절하였다. 화학기상증착법(CVD)에 의해 합성한 단일층 그래핀은 습식 전사 공정을 통해 원하는 기판에 전사되었다. PEI에 의한 계면 도핑을 유도하기 위하여, 소수성의 그래핀 표면을 산소 플라즈마 처리를 통해 결함을 최소화하면서 친수성으로 제어하였다. PEI 도핑 효과를 전계효과트랜지스터(FET)를 이용하여 확인하였다. PEI 도핑에 의해서 CVD 그래핀의 TCR 값이 30~50℃의 온도 범위에서 -0.49(±0.03)%/K로 향상된 것을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.239-240
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• 2008

As semiconductor devices are scaled down for better performance and more functionality, the Cu-based interconnects suffer from the increase of the resistivity of the Cu wires. The resistivity increase, which is attributed to the electron scattering from grain boundaries and interfaces, needs to be addressed in order to further scale down semiconductor devices [1]. The increase in the resistivity of the interconnect can be alleviated by increasing the grain size of electroplating (EP)-Cu or by modifying the Cu surface [1]. Another possible solution is to maximize the portion of the EP-Cu volume in the vias or damascene structures with the conformal diffusion barrier and seed layer by optimizing their deposition processes during Cu interconnect fabrication, which are currently ionized physical vapor deposition (IPVD)-based Ta/TaN bilayer and IPVD-Cu, respectively. The use of in-situ etching, during IPVD of the barrier or the seed layer, has been effective in enlarging the trench volume where the Cu is filled, resulting in improved reliability and performance of the Cu-based interconnect. However, the application of IPVD technology is expected to be limited eventually because of poor sidewall step coverage and the narrow top part of the damascene structures. Recently, Ru has been suggested as a diffusion barrier that is compatible with the direct plating of Cu [2-3]. A single-layer diffusion barrier for the direct plating of Cu is desirable to optimize the resistance of the Cu interconnects because it eliminates the Cu-seed layer. However, previous studies have shown that the Ru by itself is not a suitable diffusion barrier for Cu metallization [4-6]. Thus, the diffusion barrier performance of the Ru film should be improved in order for it to be successfully incorporated as a seed layer/barrier layer for the direct plating of Cu. The improvement of its barrier performance, by modifying the Ru microstructure from columnar to amorphous (by incorporating the N into Ru during PVD), has been previously reported [7]. Another approach for improving the barrier performance of the Ru film is to use Ru as a just seed layer and combine it with superior materials to function as a diffusion barrier against the Cu. A RulTaN bilayer prepared by PVD has recently been suggested as a seed layer/diffusion barrier for Cu. This bilayer was stable between the Cu and Si after annealing at $700^{\circ}C$ for I min [8]. Although these reports dealt with the possible applications of Ru for Cu metallization, cases where the Ru film was prepared by atomic layer deposition (ALD) have not been identified. These are important because of ALD's excellent conformality. In this study, a bilayer diffusion barrier of Ru/TaCN prepared by ALD was investigated. As the addition of the third element into the transition metal nitride disrupts the crystal lattice and leads to the formation of a stable ternary amorphous material, as indicated by Nicolet [9], ALD-TaCN is expected to improve the diffusion barrier performance of the ALD-Ru against Cu. Ru was deposited by a sequential supply of bis(ethylcyclopentadienyl)ruthenium [Ru$(EtCp)_2$] and $NH_3$plasma and TaCN by a sequential supply of $(NEt_2)_3Ta=Nbu^t$ (tert-butylimido-trisdiethylamido-tantalum, TBTDET) and $H_2$ plasma. Sheet resistance measurements, X-ray diffractometry (XRD), and Auger electron spectroscopy (AES) analysis showed that the bilayer diffusion barriers of ALD-Ru (12 nm)/ALD-TaCN (2 nm) and ALD-Ru (4nm)/ALD-TaCN (2 nm) prevented the Cu diffusion up to annealing temperatures of 600 and $550^{\circ}C$ for 30 min, respectively. This is found to be due to the excellent diffusion barrier performance of the ALD-TaCN film against the Cu, due to it having an amorphous structure. A 5-nm-thick ALD-TaCN film was even stable up to annealing at $650^{\circ}C$ between Cu and Si. Transmission electron microscopy (TEM) investigation combined with energy dispersive spectroscopy (EDS) analysis revealed that the ALD-Ru/ALD-TaCN diffusion barrier failed by the Cu diffusion through the bilayer into the Si substrate. This is due to the ALD-TaCN interlayer preventing the interfacial reaction between the Ru and Si.

• 한국진공학회지
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• 제10권2호
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• pp.234-240
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• 2001

본 연구에서는 Mg을 첨가한 Cu-alloy에 의해 TiN의 확산방지능력을 향상시키고자 하였다. Cu(Mg) 박막은 대기노출시킨 TiN박막위에 증착되었으며 열처리시 Cu 박막내의 Mg은 TiN의 표면에 있는 산소와 반응하여 매우 얇은(~100 $\AA$) MgO를 형성하게되고 MgO에 의해 TiN의 확산방지능력은 Cu(4.5 at.%Mg)의 경우 $800^{\circ}C$까지 향상됨을 알 수 있었다. 그러나 Cu(Mg) a]toy는 TiN위에서 접착특성이 좋지 않기 때문에 TiN을 $O_2$plasma 처리하였으며 $O_2$ plasma 처리후 $300^{\circ}C$ 진공열처리를 통해 접착력이 크게 향상되는 것을 알 수 있었다. 이는 $O_2$ plasma 처리에 의해 TiN표면에 Mg과 반응할 수 있는 산소의 양이 증가하는 데 기인하며 이에 따라 Mg의 계면이동이 크게 증가되어 치밀한 MgO가 형성됨을 확인하였다. 그리고 $O_2$ plasma 처리시 RF power를 증가시키면 계면으로 이동하는 Mg의 양이 오히려 감소하였고 이것은 TiN의 표면이 $TiO_2$로 변하여 Mg과 결합할 수 있는 산소의 양이 상대적으로 감소하였기 때문인 것으로 생각된다. 또한 접착층으로서 Si을 50$\AA$ 증착하여 접착력을 크게 향상시켰으며 Si 증착에 의한 TiN의 확산방지능력은 감소되지 않는 것을 알 수 있었다.

• 한국진공학회지
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• 제16권3호
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• pp.197-204
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• 2007

p-형 실리콘 기판 위에 수 ${\AA}$ 두께의 어븀 금속을 증착하고, 후열처리 과정을 통하여 어븀-실리사이드/p-형 실리콘 접합을 형성하였다. 초고진공 자외선 광전자 분광 실험을 통하여 증착한 어븀의 두께에 따라 어븀-실리사이드의 일함수가 4.1 eV까지 급하게 감소하는 것을 관찰하였으며, X-ray 회절 실험에 의하여 형성된 어븀 실리사이드가 주로 $Er_5Si_3$상으로 구성되어 있음을 밝혔다. 또한, 어븀-실리사이드/p-형 실리콘 접합에 알루미늄 전극을 부착하여 쇼트키 다이오드를 제작하고, 전류전압 곡선을 측정하여 쇼트키 장벽의 높이를 산출하였다. 산출된 쇼트키 장벽의 높이는 $0.44{\sim}0.78eV$이었으며 어븀 두께 변화에 따른 상관 관계를 찾기 어려웠다. 그리고 이상적인 쇼트키 접합을 가정하고 이미 측정한 일함수로부터 산출한 쇼트키 장벽의 높이는 전류-전압 곡선으로부터 산출한 값에 크게 벗어났으며, 이는 어븀-실리사이드가 주로 $Er_5Si_3$ 상으로 구성되어 있고, $Er_5Si_3/p-$형 실리콘 계면에 존재하는 고밀도의 계면 상태에 기인한 것으로 사료된다.

• 마이크로전자및패키징학회지
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• 제21권3호
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• pp.25-29
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• 2014

본 연구에서는 친환경적이고, 보관수명이 1년 이상이며, 부식특성이 좋은 플라즈마 유기막 표면처리에 대한 솔더링 특성을 기존 표면처리법인 OSP와 비교하였다. 플라즈마 표면처리는 할로겐계 전구체를 사용하여 CVD 방법으로 증착하였고, 증착두께는 20 nm이었다. 본 연구에서 사용된 솔더 조성은 Sn-3.0 wt%Ag-0.5 wt%Cu이었다. 염수분무시험에서 플라즈마 표면처리 유기막은 OSP보다 우수한 부식 저항성을 나타내었다. 멀티리플로우 조건에서 플라즈마 표면처리는 OSP보다 우수한 솔더 퍼짐성을 나타내었다. 솔더링 후 단면 미세조직을 분석한 결과, 플라즈마 표면처리와 OSP시편 모두 유사한 금속간화합물층 두께 및 형상을 갖고 있었다. 플라즈마 표면처리와 OSP 모두 유사한 접합강도를 가지고 있었다.

• 한국재료학회지
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• 제11권8호
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• pp.641-646
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• 2001

$650^{\circ}C$에서 Co(η$^{5}$ $V_{5}$ $H_{5}$ ) (CO)$_2$의 반웅성.화학기상증착법에 의해 도핑되지 않은 다결정실리콘 위에 $CoSi_2$충이 직접 (in-situ) 성장되었고 이 $CoSi_2$층들의 열적안정성을 $800~1000^{\circ}C$의 온도구간에서 조사하였다. 직접 성장 방법에 의해 성장된 $CoSi_2$충은 표면에 평행한 (111) 면의 면적이 큰 결정립들을 가지는 반면에, $CoSi_2$가 먼저 형성되고 $CoSi_2$로 상변태되는 기존의 두단계 성장 방법에 의해 성장된 CoSi$_2$충은 표면에 평행한 (111) 면을 가지는 결정립들이 거의 없었다. 직접 성장 방법에 의해 성장된 $CoSi_2$층의 열적 안정성은 기존의 두 단계 성장 방법에 의해 성장된 $CoSi_2$층의 열적안정성보다 개선되어 열화 온도가 $100^{\circ}C$정도 더 높았다. 큰 결정립의 다결정실리론 기판 위에서 직접 성장된 $CoSi_2$충은 $950^{\circ}C$에서 열처리한 후에도 안정했다. 직접 성장에 의한 열적 안정성의 개선 효과는 다결정실리콘 기판의 결정립의 크기가 작을 때 두드러졌다. 직접 성장된 $CoSi_2$층의 열적 안정성 개선의 주된 원인은 다결정실리콘의 각 결정립들 위에 유사에피 성장을 하면서 자라난 $CoSi_2$ 결정립들이 균일한 $CoSi_2$층을 형성하여 이것이 계의 계면에너지를 낮추기 때문이라고 사료된다.