• Title/Summary/Keyword: Interface trap charge density distribution

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Interface trap density distribution in 3D sequential Integrated-Circuit and Its effect (3차원 순차적 집적회로에서 계면 포획 전하 밀도 분포와 그 영향)

  • Ahn, TaeJun;Lee, Si Hyun;Yu, YunSeop
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.12
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    • pp.2899-2904
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    • 2015
  • This paper introduces about the effect on $I_{DS}-V_{GS}$ characteristic of transistor that interface trap charge is created by damage due to heat in a 3D sequential inverter. A interface trap charge distribution in oxide layer in a 3D sequential inverter is extracted using two-dimensional device simulator. The variation of threshold voltage of top transistor according to the gate voltage variation of bottom transistor is also described in terms of Inter Layer Dielectric (ILD) length of 3D sequential inverter, considering the extracted interface trap charge distribution. The extracted interface trap density distribution shows that the bottom $HfO_2$ layer and both the bottom and top $SiO_2$ layer were relatively more affected by heat than the top $HfO_2$ layer with latest process. The threshold voltage variations of the shorter length of ILD in 3D sequential inverter under 50nm is higher than those over 50nm. The $V_{th}$ variation considering the interface trap charge distribution changes less than that excluding it.

Interface Trap Effects on the Output Characteristics of GaN Schottky Barrier MOSFET (GaN Schottky Barrier MOSFET의 출력 전류에 대한 계면 트랩의 영향)

  • Park, Byeong-Jun;Kim, Han-Sol;Hahm, Sung-Ho
    • Journal of Sensor Science and Technology
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    • v.31 no.4
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    • pp.271-277
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    • 2022
  • We analyzed the effects of the interface trap on the output characteristics of an inversion mode n-channel GaN Schottky barrier (SB)-MOSFET based on the Nit distribution using TCAD simulation. As interface trap number density (Nit) increased, the threshold voltage increased while the drain current density decreased. Under Nit=5.0×1010 cm-2 condition, the threshold voltage was 3.2 V for VDS=1 V, and the drain current density reduced to 2.4 mA/mm relative to the non-trap condition. Regardless of the Nit distribution type, there was an increase in the subthreshold swing (SS) following an increase in Nit. Under U-shaped Nit distribution, it was confirmed that the SS varied depending on the gate voltage. The interface fixed charge (Qf) caused an shift in the threshold voltage and increased the off-state current collectively with the surface trap. In summary, GaN SB-MOSFET can be a building block for high power UV optoelectronic circuit provided the surface state is significantly reduced.

Analysis of Trap Dependence on Charge Trapping Layer Thickness in SONOS Flash Memory Devices Based on Charge Retention Model (전하보유모델에 기초한 SONOS 플래시 메모리의 전하 저장층 두께에 따른 트랩 분석)

  • Song, Yu-min;Jeong, Junkyo;Sung, Jaeyoung;Lee, Ga-won
    • Journal of the Semiconductor & Display Technology
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    • v.18 no.4
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    • pp.134-137
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    • 2019
  • In this paper, the data retention characteristics were analyzed to find out the thickness effect on the trap energy distribution of silicon nitride in the silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices. The nitride films were prepared by low pressure chemical vapor deposition (LPCVD). The flat band voltage shift in the programmed device was measured at the elevated temperatures to observe the thermal excitation of electrons from the nitride traps in the retention mode. The trap energy distribution was extracted using the charge decay rates and the experimental results show that the portion of the shallow interface trap in the total nitride trap amount including interface and bulk trap increases as the nitride thickness decreases.

Characterization of the Vertical Position of the Trapped Charge in Charge-trap Flash Memory

  • Kim, Seunghyun;Kwon, Dae Woong;Lee, Sang-Ho;Park, Sang-Ku;Kim, Youngmin;Kim, Hyungmin;Kim, Young Goan;Cho, Seongjae;Park, Byung-Gook
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.2
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    • pp.167-173
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    • 2017
  • In this paper, the characterization of the vertical position of trapped charges in the charge-trap flash (CTF) memory is performed in the novel CTF memory cell with gate-all-around structure using technology computer-aided design (TCAD) simulation. In the CTF memories, injected charges are not stored in the conductive poly-crystalline silicon layer in the trapping layer such as silicon nitride. Thus, a reliable technique for exactly locating the trapped charges is required for making up an accurate macro-models for CTF memory cells. When a programming operation is performed initially, the injected charges are trapped near the interface between tunneling oxide and trapping nitride layers. However, as the program voltage gets higher and a larger threshold voltage shift is resulted, additional charges are trapped near the blocking oxide interface. Intrinsic properties of nitride including trap density and effective capture cross-sectional area substantially affect the position of charge centroid. By exactly locating the charge centroid from the charge distribution in programmed cells under various operation conditions, the relation between charge centroid and program operation condition is closely investigated.

Numerical Analysis about the Time Characteristics of Space Charge Distribution and Measured Current in LDPE (LDPE에서 공간전하분포와 측정전류의 시간특성에 대한 수치해석)

  • Hwang, Bo-Seung;Park, Dae-Hui;Nam, Seok-Hyeon;Gwon, Yun-Hyeok;Han, Min-Gu
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.49 no.9
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    • pp.502-509
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    • 2000
  • In this paper in order to evaluat quantitavely the formation mechanism of space charge and its effects on the conduction characteristics in LDPE we have carried out the numerical analysis on the basis of experimental results of space charge distribution cathode field and current with time which had been simultaneously measured at applied field of 50kV/mm and room temperature. As the models for numerical analysis we employ the Richarson-Schottky theory for charge injection from electrode into LDPE and the band-tail conduction at crystalline regions and the hopping conduction by traps which mainly exist at the interface regions of crystalline-amorphous region for charge transport in LDPE. Futhermore in order to investigate the influence of physical parameters on the time characteristcs of space charge distribution and measured current we have changed the values of trap density activation energies for charge injection and transport and have analyzed their effects.

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A Novel Atomic Layer Deposited Al2O3 Film with Diluted NH4OH for High-Efficient c-Si Solar Cell

  • Oh, Sung-Kwen;Shin, Hong-Sik;Jeong, Kwang-Seok;Li, Meng;Lee, Horyeong;Han, Kyumin;Lee, Yongwoo;Lee, Ga-Won;Lee, Hi-Deok
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.1
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    • pp.40-47
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    • 2014
  • In this paper, $Al_2O_3$ film deposited by thermal atomic layer deposition (ALD) with diluted $NH_4OH$ instead of $H_2O$ was suggested for passivation layer and anti-reflection (AR) coating of the p-type crystalline Si (c-Si) solar cell application. It was confirmed that the deposition rate and refractive index of $Al_2O_3$ film was proportional to the $NH_4OH$ concentration. $Al_2O_3$ film deposited with 5 % $NH_4OH$ has the greatest negative fixed oxide charge density ($Q_f$), which can be explained by aluminum vacancies ($V_{Al}$) or oxygen interstitials ($O_i$) under O-rich condition. $Al_2O_3$ film deposited with $NH_4OH$ 5 % condition also shows lower interface trap density ($D_{it}$) distribution than those of other conditions. At $NH_4OH$ 5 % condition, moreover, $Al_2O_3$ film shows the highest excess carrier lifetime (${\tau}_{PCD}$) and the lowest surface recombination velocity ($S_{eff}$), which are linked with its passivation properties. The proposed $Al_2O_3$ film deposited with diluted $NH_4OH$ is very promising for passivation layer and AR coating of the p-type c-Si solar cell.