• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.12 no.2
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• pp.62-68
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• 1998

In this paper, we proposed the design of the intelligent traffic control system by using multiprocessor architecture. The inter-processor communication of the architecture is implemented by sharing the serial communication channel. In comparing the conventional traffic control system using single processor architecture, the proposed system uses multiple processors controlling the sub systems such as the signal lights, traffic measurement unit, auxiliary signal lights and peripherals. The main processor controls the communication among the processors and the communication protocol link to the central control center at remote site. The proposed architecture reduces the load and simplifies the program of each processor and enables the real time processing of the add-on features of intelligent traffic control systems. The architecture is implemented and the common channel inter-processor communications and the real time operation is experimented .experimented .

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.6
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• pp.599-606
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• 1987

Giving a high degree of intelligence to the electronic equipments such as communication system is the general trend of nowadays. Therefore the multi-processor will be required in a single system and the switch gives an example of it. In this paper, "Reserved Bus" is proposed as the interprocessor communication method applicable to such system which has multi-processor in the limited space. The performance of proposed method is also analyzed. analyzed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8A
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• pp.1213-1222
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• 2000

We have considered and developed a subsystem of switching system which provides Internet access service, taking into considerations of traffic and quality problems. In this paper, Internet subsystem with a structure and function has been presented that turns the switching system into the optimized gateway between switching system and Internet. And, this paper developed simulation model and analyzed a performance of inter-processor communication unit which practically functions as an Internet traffic transfer.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.7
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• pp.1335-1345
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• 1994

In this paper, the performance analysis of Inter-Processor Communication Network(IPCN) in a large-capacity digital switching system, TDX-10, is presented. The simulation model of IPCN is developed using discrete event model of SLAM II. The simulation results of maximum buffer length and mean waiting times at each node, and utilization of D-bus are derived. Finally, the maximum call handling capacity of IPCN is obtained by taking link speed into consideration.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.1
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• pp.50-57
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• 2000

By supporting wireless communication technology, there is gradually expansion of the commercial application for Wireless Local Loop(WLL) technology, which is to replace existing telephone line with wireless one. The WLL system application helps a operator to have merits of the installation and maintenance of line and also a subscriber to make a high speed value-added service. As mentioned above reasons for both sides, many manufactories and operators are concerned with development and application respectively. This paper presents hardware implementation of Radio Port Controller(RPC) and also describes the system configuration, functions, and Inter Processor Communication(IPC) structure of RPC. We performed inter-module communication test via IPC backplane bus. And inter-module integration test also completed through data communication and signal waveform measurement repeatedly.

• The KIPS Transactions:PartC
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• v.10C no.1
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• pp.71-76
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• 2003

Internet traffic is getting tremendously heavier due to the exponential growth of the Internet users, the spread of the E-commerce and the network games. High-speed routers for fast packet forwarding are commercially available to satisfy the growing bandwidth. A high-speed router, which has the decentralized multiprocessing architecture for IP and routing functions, consists of host processors, line interfaces and switch fabrics. In this paper, we propose a software architecture tuned for high-speed non-forwarding packet manipulation. IPCMP (Inter-Processor Communication Message Protocol), which is a mechanism for IPC (Inter-Processor Communication), is also proposed and implemented as well. Proposed IPC mechanism results in faster packet-processing rate by 10% as compared to the conventional IPC mechanism using UDP/IP.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.3
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• pp.177-183
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• 2018

Currently, digital signal processing systems are used extensively in image processing, audio processing, filtering, and equalizations, etc. In addition, the importance of DRAM, which has a great influence on the performance of an digital signal processor has been increased, making research on DRAM actively conducted in industry and academia. Therefore, it is important to have a more accurate DRAM model in order to obtain reliable results when evaluating the performance of a digital signal processor through simulation. In this paper, we developed a digital signal processor simulator capable of inter-working with a DRAM simulator. With the simulator, we analyzed the influence of the DRAM model which operates correctly on a cycle-by-cycle basis, on the performance of the digital signal processor by using the UTDSP digital signal benchmark.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.29-35
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• 1998

This paper describes architectures and design of a SIMD type parallel image processing chip called SliM-II. The chiphas a linear array of 64 processing elements (PEs), operates at 30 MHz in the worst case simulation and gives at least 1.92 GIPS. In contrast to existing array processors, such as IMAP, MGAP-2, VIP, etc., each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU operation, data I/O, and inter-PE communication simulataneously in a single instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel move between the register file and on-chip memory as in DSP chips, SliM-II can greatly reduce the inter-PE communication overhead, due to the idea a sliding, which is a technique of overlapping inter-PE communication with computation. Moreover, the bandwidth of data I/O and inter-PE communication increases due to bit-parallel data paths. We used the COMPASS$^{TM}$ 3.3 V 0.6.$\mu$m standrd cell library (v8r4.10). The total number of transistors is about 1.5 muillions, the core size is 13.2 * 13.0 mm$^{2}$ and the package type is 208 pin PQ2 (Power Quad 2). The performance evaluation shows that, compared to a existing array processors, a proposed architeture gives a significant improvement for algorithms requiring multiplications.s.

• ETRI Journal
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• v.17 no.1
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• pp.23-36
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• 1995

We present a performance evaluation model of cell reassembly mechanism in an ATM switching system. An ATM switching system may be designed so that communications between processors of its control part can be performed via its switching network rather than a separate inter-processor communications network. In such a system, there should be interface to convert inter-processor communication traffic from message format to cell format and vice versa, that is, mechanisms to perform the segmentation and reassembly sublayer. In this paper, we employ a continuous-time Markov chain for the performance evaluation model of cell reassembly mechanism with individual buffering, judicially defining the states of the mechanism. Performance measures such as message loss probability and average reassembly delay are obtained in closed forms. Some numerical illustrations are given for the performance analysis and dimensioning of the cell reassembly mechanism.

• Electronics and Telecommunications Trends
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• v.37 no.3
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• pp.41-51
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• 2022

This article presents an overview of the key technologies in the communications payload of broadband LEO satellite communications systems. In recent years, new developments have been realized for LEO satellite communications. SpaceX's Starlink, a technology leader in this field, offers premium services with satellites carrying in-house developed communications payloads. OneWeb, Amazon, Telesat, and Boeing are also developing LEO satellite communications payloads. The communications payload consists of user link antennas, inter-satellite link communications equipment, feeder link antennas, and a digital processor. Highly sophisticated technologies of compact active phased array antennas for generating multiple hopping beams and light laser communication equipment for ultra-high-speed inter-satellite communication will be applied to next- generation payloads.