• Korean Journal of Poultry Science
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• v.40 no.2
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• pp.157-162
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• 2013

Both ODC and PRDM16 genes were known to be associated with body weight traits in chicken. These two genes were located on GGA3 and GGA21, respectively, where the QTLs of body weights are located. Therefore, the objectives of this study were to identify the SNPs in these two genes and their associations with body weight traits in Korean native chicken. Fluidigm Dynamic Array integrated fluidic circuits (IFCs) assay was used to genotype 7 SNPs consisting g.-353C>T, g.2136A>G, g.2524T>C, g.3607C>T SNPs of the ODC gene, and g.182216C>T, g.182290A>T, g.182491A>T SNPs of the PRDM16 gene. Statistical analysis showed that g.2136A>G SNP of the ODC was associated with body weight at 20 weeks of age and slaughter weight, and g.3607C>T SNP of the ODC was associated with body weight at 2 weeks of age. Association between g.182216C>T SNP of the PRDM16 and body weight at 12 weeks of age has also been revealed. In addition, g.182491A>T SNP of PRDM16 has significant correlation with body weight (BW) at 8 weeks, BW at 10 weeks and BW at 14 weeks of age. These results suggested that both ODC and PRDM16 could be strong candidate genes for body weight traits in Korean native chicken.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.12
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• pp.656-664
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• 2007

Field-Programmable Gate Arrays (FPGAs) are a revolutionary new type of user-programmable integrated circuits that provide fast, inexpensive access to customized VLSI. However, as the target application speed increases, power-consumption and wire-delay on interconnection become more critical factors during programming an FPGA. Especially, the interconnection of the FPGA consumes 65% of the total FPGA power consumption. A previous research show that if the length of interconnection is shirked, power-consumption can be reduced because an interconnection has a lot of effect on power-consumption. For solving this problem that reducing the number of wires routed, the three dimension FPGA is proposed. However, this structure physical wires and an area of switches is increased by making topology complex. This paper propose a novel FPGA architecture that modifies the three dimension FPGA and compare the number of interconnection of Virtex II and 3D FPGA with the proposed FPGA architecture using the FPGA Editor of Xilinx ISE and a global routing and length estimation program.

• Journal of the Korea Computer Industry Society
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• v.2 no.2
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• pp.219-228
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• 2001

This paper presents the implementation of comparator which are Fail-Safe with respect to faults caused by any single physical defect likely to occur in NMOS and CMOS integrated circuit. The goal is to use it at the Fail-Safe system. First, a new fault model for PLA(Programmable Logic Array) is presented. This model reflects several physical defects in VLSI circuits. It focuses on designs based on PLA because VLSI chips are far too complex to allow detailed analysis of all the possible physical defects that can occur and of the effects on the operation of the circuit. Second, this paper show that these design, which was implemented with 2 level AND_ORor NOR-NOR circuit, are optimal in term of size. And it also present a formal proof that a comparator implemented as NOR-NOR PLA, based on these design, is self-testing with respect to most single faults in the presented fault model. Finally, it discuss the application of the self-testing comparator as a building block for implementing Fail-Safe Adder.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.301-306
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• 2005

In this paper, a gain-boosting charge pump(CP) and a latch type voltage controlled oscillato.(VCO) with voltage controlled resistor(VCR) were proposed. The gain-boosting CP achieves good .current matching of less than 11$mu$V voltage difference between 43$mu$V and 32$mu$V in its output range from 0.8V to 2.3V. The VCO with VCR shows good linear characteristics over the range from 1V to 3V. The fabricated VCO exhibits -108dBc/Hz phase noise at a 100kHz and is comparable to that of the integrated LC-tank oscillator. The phase locked loop(PLL) with new circuits was simulated in a 0.35$mu$m CMOS process and showed 150$mu$s locking time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.7
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• pp.1445-1451
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• 2005

Home-Network is an integrated network of the PC and all electric home appliances in the home so that they can communicate with each other. In the 21th century, here are various technology for Home Network environment such as HomePNA, IEEE 1394, Ethernet Lan and Bluetooth. For Home Network construction, generally, the standard series interface 'RS232' is used to make communication possible between electric home appliances. However Home network using RS232 has a problem. That is, All machines have to be connected to each other with RS232 using Point-to-Point mode. In this case, the system becomes complicated because we have to use circuits as much as there are machines and increased expenses. To improve this problem, In this thesis, designed home network using RS422 Multi-drop mode serial communication and controled it with embedded linux system. And connected RS422 with motors and sensors using PIC to make the home network virtual environment.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.403-406
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• 1999

The influence of temperature variation (25～125$^{\circ}C$) on poly-Si thin-film transistors (TFT's) was investigated by examining the electrical properties change of poly-Si films formed by solid phase crystallization (SPC). The n-channel poly-Si TFT's fabricated by SPC with channel length of 1.5 and loon ,respectively, exhibit good characteristics with a high ${\mu}$$\sub$FE/ ($\geq$82 and $\geq$60$\textrm{cm}^2$/V-s in 1.5 and 10$\mu\textrm{m}$, respectively), low V$\sub$t/, ($\leq$1.52 and $\leq$ 2.75V in 1.5 and 10$\mu\textrm{m}$, respectively), low S$\sub$t/, and good ON-OFF characteristics in spite of temperature variation. Thus, poly-Si films formed by SPC can be applied for the application to poly-Si TFT liquid crystal display with peripheral integrated circuits.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.943-949
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• 2010

This paper presents some improvements on VLSI implementation of lifting-based 9/7 wavelet transform by optimization hardware multiplication. The proposed solution requires less logic area and power consumption without performance loss compared to previous wavelet filter structure based on lifting scheme. This paper proposes a better approach to the hardware implementation using Lefevre algorithm based on extensions of Pattern search methods. To compare the proposed structure to the previous solutions on full multiplier blocks, we implemented them using Verilog HDL. For a hardware implementation of the two solutions, the logical synthesis on 0.18 um standard cells technology show that area, maximum delay and power consumption of the proposed architecture can be reduced up to 51%, 43% and 30%, respectively, compared to previous solutions for a 200 MHz target clock frequency. Our evaluation show that when design VLSI chip of lifting-based 9/7 wavelet filter, our solution is better suited for standard-cell application-specific integrated circuits than prior works on complete multiplier blocks.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.4
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• pp.285-296
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• 2005

Reduced pressure chemical vapor deposition technology has been used to study SiGe heterostructure epitaxy and device issues, including SiGe relaxed buffers, proper control of Ge component and crystalline defects, two dimensional delta doping, and their influence on electrical properties of devices. From experiments, 2D profiles of B and P presented FWHM of 5 nm and 20 nm, respectively, and doses in 5×10/sup 11/ ∼ 3×10/sup 14/ ㎝/sup -2/ range. The results could be employed to fabricate SiGe/Si heterostructure field effect transistors with both Schottky contact and MOS structure for gate electrodes. I-V characteristics of 2D P-doped HFETs revealed normal behavior except the detrimental effect of crystalline defects created at SiGe/Si interfaces due to stress relaxation. On the contrary, sharp B-doping technology resulted in significant improvement in DC performance by 20-30 ％ in transconductance and short channel effect of SiGe HMOS. High peak concentration and mobility in 2D-doped SiGe heterostructures accompanied by remarkable improvements of electrical property illustrate feasible use for nano-sale FETs and integrated circuits for radio frequency wireless communication in particular.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.3.1-3.1
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• 2011

Over the past decade, the major efforts for lowering the cost of electronics has been devoted to increasing the packaging efficiency of the integrated circuits (ICs), which is defined by the ratio of all devices on system-level board compared to the area of the board, and to working on a larger but cheaper substrates. Especially, in flexible electronics, the latter has been the favorable way along with using novel nanomaterials that have excellent mechanical flexibility and electrical properties as active channel materials and conductive films. Here, the tool for achieving large area patterning is by printing methods. Although diverse printing methods have been investigated to produce highly-aligned structures of the nanomaterials with desired patterns, many require laborious processes that need to be further optimized for practical applications, showing a clear limit to the design of the nanomaterial patterns in a large scale assembly. Here, we demonstrate the alignment of highly ordered and dense silicon (Si) NW arrays to anisotropically etched micro-engraved structures using a simple evaporation process. During evaporation, entropic attraction combined with the internal flow of the NW solution induced the alignment of NWs at the corners of pre-defined structures. The assembly characteristics of the NWs were highly dependent on the polarity of the NW solutions. After complete evaporation, the aligned NW arrays were subsequently transferred onto a flexible substrate with 95% selectivity using a direct gravure printing technique. As proof-of-concept, flexible back-gated NW field effect transistors (FETs) were fabricated. The fabricated FETs had an effective hole mobility of 0.17 $cm2/V{\cdot}s$ and an on/off ratio of ${\sim}1.4{\times}104$. These results demonstrate that our NW gravure printing technique is a simple and effective method that can be used to fabricate high-performance flexible electronics based on inorganic materials.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.12
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• pp.1174-1180
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• 2011

Field Programmable Gate Array(FPGA)s are replacing traditional integrated circuits for space applications due to their lower development cost as well as reconfigurability. However, they are very sensitive to single event upset (SEU) caused by space radiation environment. In order to mitigate the SEU, on-board computer of STSAT-3 employed a triple modular redundancy(TMR) and scrubbing scheme. Experimental results showed that upset threshold energy was improved from 10.6 MeV to 20.3 MeV when the TMR and the scrubbing were applied to the on-board computer. Combining the experimental results with the orbit simulation results, calculated bit-flip rate of on-board computer is 1.23 bit-flips/day assuming in the worst case of STSAT-3 orbit.