• Structural Engineering and Mechanics
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• v.5 no.5
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• pp.635-644
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• 1997

The paper reviews the implementation and evaluation of exact methods for the computation of transcendental structural eigenvalues, i.e., critical buckling loads and natural frequencies of undamped vibration, on multiple instruction, multiple data parallel computers with distributed memory. Coarse, medium and fine grain parallel methods are described with illustrative examples. The methods are compared and combined into hybrid methods whose performance can be predicted from that of the component methods individually. An indication is given of how performance indicators can be presented in a generic form rather than being specific to one particular parallel computer. Current extensions to permit parallel optimum design of structures are outlined.

• Korean Journal of Computational Design and Engineering
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• v.5 no.4
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• pp.327-335
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• 2000

The spent fuel rod extracting machine is automatically operated in high radioactive environment, so high reliability of operation is required. In this paper, to enhance the reliability of this machine by providing a close monitoring capability. a real time graphic simulation method is suggested. This method utilizes conventional IGRIP (Interactive Graphics Robot Instruction Program) 3D graphic simulation tool to visualize and simulate the 3D graphic model of this machine. Also, the dedicated protocol is defined for transmission of the operational data of the machine. The real time graphic simulation is realized by developing the socket module between a graphic workstation and a machine control computer through the TCP/IP network and by dividing the 3D graphic simulation GSL(Graphic Simulation Language) program as a small sized sub routine. The suggested method is implemented while automatically operating the rod extracting machine. The result of implementation shows that the real time 3D graphic simulation is well synchronized with the actual machine according to the operational data.

• Journal of IKEEE
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• v.11 no.4
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• pp.358-363
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• 2007

This paper presents a floating point unit(FPU) with 3 stages for a 3D graphics shader engine. It targeted to accelerate 3D graphics in portable device environments. In order to design a balanced architecture for a shader engine, we analyzed shader assembly instructions and estimated the performance of FPU with the method we propose. The proposed unit handles 4-dimensional data through separated two paths that are lead to general operation module and special function module. The proposed FPU is compiled as a form of the cascade FPU with 3 stages to efficiently handle a matrix operation with relatively low hardware overhead. Except some complex instructions that are executed using macro instructions, all instructions complete an operation in a single instruction cycle at 100MHz frequency. A special function module performs all operations in a single clock cycle using the Newton Raphson method with the look-up table.

• The Research Journal of the Costume Culture
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• v.11 no.4
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• pp.500-512
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• 2003

This study was performed to help on the activation plan the purchase of apparel by shopping(catalog/TV/Internet) through investigating and analyzing elements related with apparel purchasing practice, purchasing satisfaction degree, and information demand. The subjects were 165 housewives residing in Cheongju who had bought apparel through home shopping more than once. The questionnaire survey was conducted from July to August, 2002. The results of this study were as follows: 1) Housewives had most a lot of occasions that purchased clothing through TV shopping among home shopping method. 2) Major clothing items that purchased through home shopping were underwear and casual wear. 3) Satisfaction for apparel product purchased via home shopping was difference partially item wise. 4) Respondents were satisfied with design, color, sewing state, but dissatisfied with size and materials. 5) When purchasing apparel through home shopping, respondents recognized the necessity of information on size, exchange/refund/returned policy, color, design, resolution of the product picture, care of instruction, texture and detail of apparel.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.365-369
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• 2002

In this paper, DC motor controller has been designed by using SoC. SoC is short for System on a chip. This is a methodology that both a processor and some applications are integrated in a chip. In order to design this system based on SoC, PIC 16C57 has been selected as a processor because it has not too many instruction sets and simple data path named a harvard structure. And motor control module has been programmed by using VHDL. The advantages of the design based on SoC are as follows: simple structure, high speed working, easily verifying and simulating the system.

• Journal of Electrical Engineering and information Science
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• v.2 no.4
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• pp.1-7
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• 1997

A multiprocessor microprocessor named SMPC(scaleable multiprocessor chip) that contains tow IU (integer unit) is presented in this paper. It can execute multiple instructions from several tasks exploiting task-level parallelism that is free from instruction dependencies, and provide high performance and throughput on both single program and multiprogramming environments. the IU is a 32-bit scalar processor expecially designed to boost up the performance of string manipulations which are frequently used in RDBMS(relational data base management system) applications. A memory management unit and a data cache shared by two IUs improve the performance and reduce the chip area required. ETH SMPC is implemented in VLSI circuit by custom design and automated design tools.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.2
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• pp.83-88
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• 2015

Core-A is 32-bit synthesizable processor core with a unique instruction set architecture (ISA). In this paper, the Core-A ISA is introduced with discussion of useful features and the development environment, including the software tool chain and hardware on-chip debugger. Core-A is described using Verilog-HDL and can be customized for a given application and synthesized for an application-specific integrated circuit or field-programmable gate array target. Also, the GNU Compiler Collection has been ported to support Core-A, and various predesigned platforms are well equipped with the established design flow to speed up the hardware/software co-design for a Core-A-based system.

• IE interfaces
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• v.9 no.1
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• pp.41-52
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• 1996

As part of effort to reduce the process time from design to manufacture and delivery, the concept of CE(concurrent engineering) has been applied to design process. In this research, the drawing information management system (DIMS) was developed based on CE. The system can distribute electronic documents of drawing or work instruction parallel to all reviewers simultaneously and collect their annotations through network. Mark-up functions are used for annotations on the electronic documents. DIMS is a system which integrates drawing management, engineering BOM, CAD and raster drawings, etc. In this system, a SUN workstation is interfaced with PCs by LAN. CIMCAD-2D, Image Hunter, and ORACLE RDBMS are used for CAD drawings, raster drawings, and drawing information management, respectively. As an integration tool for all the information, LINKAGE is adopted.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.9-19
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• 1997

This paper describes the design and FPGA implementation of a system control unit within a multiprocessor chip which can be used as a node processor ina massively parallel processing (MPP) caches, memory management units, a bus unit and a system control unit. Major functions of the system control unit are locking/unlocking of the shared variables of protected access, synchronization of instruction execution among four integer untis, control of interrupts, generation control of processor's status, etc. The system control unit was modeled in very high level using verilog HDL. Then, it was simulated and verified in an environment where trap handler and external interrupt controller were added. Functional blocks of the system control unit were changed into RTL(register transfer level) model and synthesized using xilinx FPGA cell library in synopsys tool. The synthesized system control unit was implemented by Xilinx FPGA chip (XC4025EPG299) after timing verification.

• Journal of the Korea Society of Computer and Information
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• v.23 no.1
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• pp.49-55
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• 2018

In this paper, we propose a design and development of instructional cards to understand the grammar of coding, solving the problems and extending the computational thinking in the robot-driven environment. First, we designed the input/output module of the robot to process the coding grammar through the function analysis of the robot. And we designed the module of command card to learn coding grammar using color sensors. We have proven the validity of the designed instruction card by examining the experts to see if it is suitable for coding grammar learning. Designed robot and command card were developed with 28 cards and sensor robot. After applying the developed robot and command card to the elementary school students, the questionnaire showed that students grow the understanding and confidence of coding. In addition, students showed an increased need for programming learning.