An On-chip Multiprocessor Miroprocessor with Shared MMU and Cache

  • Published : 1997.08.01

Abstract

A multiprocessor microprocessor named SMPC(scaleable multiprocessor chip) that contains tow IU (integer unit) is presented in this paper. It can execute multiple instructions from several tasks exploiting task-level parallelism that is free from instruction dependencies, and provide high performance and throughput on both single program and multiprogramming environments. the IU is a 32-bit scalar processor expecially designed to boost up the performance of string manipulations which are frequently used in RDBMS(relational data base management system) applications. A memory management unit and a data cache shared by two IUs improve the performance and reduce the chip area required. ETH SMPC is implemented in VLSI circuit by custom design and automated design tools.

Keywords

References

  1. Proc. 3rd Intl Conf. on Architectural Support for Programming Languages and Operating Systems Cache memories and multiprocessors tutorial notes J.Goodman
  2. The SPARC Architecture Manual
  3. Proc. ITC-CSCC VLSI design of the control unit of a 32-bit RISC integer unit J.K.Ahn;B.I.Moon;S.K.Moon;Y.H.Lee;Y.S.Lee;S.H.Yoon
  4. Proc. 23rd Intl Symp. on Computer Architecture Evaluation of design alternatives for a multiprocessor microprocessor B.A.Nayfeh;L.Hammond;K.Olukotun
  5. Digest of Papers COMPCON New CPU benchmark suites from SPEC K.M.Dixit
  6. Proc. 17th Intl Symp. on Computer Architecture APRIL : a processor architecture for multiprocessing A.Agarwal;B.H.Lim;D.Kranz;J.Kubiatowicz
  7. Proc. 3rd Intl Conf. on Architectural Support for Programming Languages and Operating Systems The effect of sharing on the cache and bus performance S.J.Eggers;R.H.Katz
  8. Proc. 22rd Intl Symp. on Computer Architecture Design of cache memories for multi-threaded dataflow architecture K.M.Kavi;A.R.Hurson;P.Patadia;E.Abraham;P.Shanmugam