• Title/Summary/Keyword: Instruction Design

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Code Size Reduction and Execution performance Improvement with Instruction Set Architecture Design based on Non-homogeneous Register Partition (코드감소와 성능향상을 위한 이질 레지스터 분할 및 명령어 구조 설계)

  • Kwon, Young-Jun;Lee, Hyuk-Jae
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.48 no.12
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    • pp.1575-1579
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    • 1999
  • Embedded processors often accommodate two instruction sets, a standard instruction set and a compressed instruction set. With the compressed instruction set, code size can be reduced while instruction count (and consequently execution time) can be increased. To achieve code size reduction without significant increase of execution time, this paper proposes a new compressed instruction set architecture, called TOE (Two Operations Execution). The proposed instruction set format includes the parallel bit that indicates an instruction can be executed simultaneously with the next instruction. To add the parallel bit, TOE instruction format reduces the destination register field. The reduction of the register field limits the number of registers that are accessible by an instruction. To overcome the limited accessibility of registers, TOE adapts non-homogeneous register partition in which registers are divided into multiple subsets, each of which are accessed by different groups of instructions. With non-homogeneous registers, each instruction can access only a limited number of registers, but an entire program can access all available registers. With efficient non-homogeneous register allocator, all registers can be used in a balanced manner. As a result, the increase of code size due to register spills is negligible. Experimental results show that more than 30% of TOE instructions can be executed in parallel without significant increase of code size when compared to existing Thumb instruction set.

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Systematic Development of Instruction for Family Life Planning of High School Curriculum for Technology and Home Economics Based on Backward Design (백워드 수업설계에 기초한 고등학교 「기술·가정」교과 '가족생활 설계' 영역의 체제적 수업개발)

  • Yoo, Se Jong;Lee, Yon Suk
    • Human Ecology Research
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    • v.56 no.1
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    • pp.33-54
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    • 2018
  • This study devised an instruction that applies the content factors of Family Life Planning to backward design by exploring the fundamental concepts of backward design and the structure of developing a systematic instruction. Furthermore, it was conducted to improve the developed instruction by examining its validity with the help of experts and to find the method of applying it to the curriculum. The lesson design of this study was as follows. 1) Making a unit outline, 2) Identifying the expected results (Shaping the objectives), 3) Deciding acceptable evidence (Planning evaluation), 4) Making a detailed blueprint for class tasks, 5) Planning learning experience, 6) Making a learning experience plan per time, 7) Checking the lesson design. Second, experts participated in this study for the internal validity test about the process of the systematic lesson development of Family Life Design based on a backward design. The results were shown to be valid because the average was 3.7 out of a perfect score 4 and the CVI of all was over 0.9. The result of the IRA was also score 1, meaning that most of the experts agreed on the results of the test. The details of the lesson design were clear at every stage and the tasks and the results of each stage were specific. This study included most of the necessary stages for a backward design.

Energy-aware Instruction Cache Design using Backward Branch Information for Embedded Processors (임베디드 시스템에서 후방 분기 명령어 정보를 이용한 저전력 명령어 캐쉬 설계 기법)

  • Yang, Na-Ra;Kim, Jong-Myon;Kim, Cheol-Hong
    • Journal of the Korea Society of Computer and Information
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    • v.13 no.6
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    • pp.33-39
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    • 2008
  • Energy efficiency should be considered together with performance when designing embedded processors. This paper proposes a new energy-aware instruction cache design using backward branch information to reduce the energy consumption in an embedded processor, since instruction caches consume a significant fraction of the on-chip energy. Proposed instruction cache is composed of two caches: a large main instruction cache and a small loop instruction cache. Proposed technique enables the selective access between the main instruction cache and the loop instruction cache to reduce the number of accesses to the main instruction cache, leading to good energy efficiency. Analysis results show that the proposed instruction cache reduces the energy consumption by 20% on the average, compared to the traditional instruction cache.

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A Study on the Change of Learning Satisfaction and Comprehension of Team Project Instruction Using Creative Capstone Design (창의적 캡스톤 디자인을 활용한 팀 프로젝트수업 운영에 따른 학습만족도 및 이해도 변화에 관한 연구)

  • Kim, Changhee
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.13 no.4
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    • pp.179-191
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    • 2017
  • The purpose of this study is to investigate the change of comprehension degree about learning satisfaction and capstone class by applying the subject which draws idea for team project task in college to creative capstone design program. The Capstone Design Program is designed to train fieldworkers with creative problem solving skills and is widely applied as a problem-solving course in team-based projects. In this paper, based on the case study of the 'fusion capstone design' operated in the first semester of 2015 ~ 2017, the capstone design course was established in the course of designing ideas for problem solving. The results of this study are as follows: First, the questionnaire about capstone design instruction process, instruction method, and learning achievement satisfaction were analyzed. As a result, understanding of capstone design was found to be higher than that of class before class, and satisfaction of performance course, method of teaching performance and learning outcome were obtained.

A Study on the Basic Design Education Using WWW (WWW를 활용한 기초디자인교육에 관한 연구)

  • 김소영;임창영
    • Archives of design research
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    • v.11 no.1
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    • pp.161-172
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    • 1998
  • The evolution of computing environments caused various dharges in our society. The change cj instruction media is one of these effects. WWW using network techndogy is regarded as a pov.powerful tool for rerrote instruction. The methods of utilizing network technologies in design instrudion and design process rould be diversified comparing with those of other general instruction. Computer graphics has been regarded as a very use!u design tool for its accuracy and rapidty. Network can help us to do creative work using cornplter graphics. The merits of this technology are sharing resources and rraking it easy to roIlaborate. Recent cxxnputer graphics instruction has some defects in oontents and methods. The oontents have a weak relationship with other industrial design subjects. From above, the purpose of this thesis is to use computer graphics and netv.urk technology for supporting basic design instruction. Virtual gallery using WWW can be a cyberspare v.tlere the evaluation of results and the exchange of information take plare. This tool makes it easier to oomrunicate and oollaborate with dassmates. A casestudy-Composition with basic objectswas exea.rted by individual for distributed asynchronous rmde. The results of this thesis are summarized for four factors. Rrst, it was easy to transform idea. Serond, student-oriented working was performed. Third, interaction among students was activated. Fourth, not only final results, but also midterm results was oonsidered for evaluation. These methods also have problems as rerent instruction methods, but it rould be used as a instruction tool to compensate for existing instruction methods.

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A Design of a 8-Thread Graphics Processor Unit with Variable-Length Instructions

  • Lee, Kwang-Yeob;Kwak, Jae-Chang
    • Journal of information and communication convergence engineering
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    • v.6 no.3
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    • pp.285-288
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    • 2008
  • Most of multimedia processors for 2D/3D graphics acceleration use a lot of integer/floating point arithmetic units. We present a new architecture with an efficient ALU, built in a smaller chip size. It reduces instruction cycles significantly based on a foundation of multi-thread operation, variable length instruction words, dual phase operation, and phase instruction's coordination. We can decrease the number of instruction cycles up to 50%, and can achieve twice better performance.

Effect of Augmented Reality Contents Based Instruction on Academic Achievement, Interest and Flow of Learning (증강현실 콘텐츠 기반 수업이 학업성취, 학습흥미, 몰입에 미치는 효과)

  • Noh, Kyung-Hee;Jee, Hyung-Keun;Lim, Suk-Hyun
    • The Journal of the Korea Contents Association
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    • v.10 no.2
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    • pp.1-13
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    • 2010
  • The purpose of this experimental study is to find out the effect of augmented reality contents based instruction on academic achievement, interest and flow of learning. The subjects were 142 students of five classes, sampled from 6th graders of an elementary school. Three classes(86 students) were taught by augmented reality based instruction and the other two classes(56 students) were taught by textbook based instruction for 2 weeks. The experimental design of the study was the pretest-posttest control group design. The results are summarized as follows: First, there is a significant difference in academic achievement between two groups. Augmented reality based instruction group accomplished higher achievement than textbook based instruction group. Second, there is no significant difference in general interest of learning between two groups. But in the interest of lessons taken by students themselves, augmented reality based instruction is more effective than textbook based instruction. Finally, there is a significant difference in learning flow between two groups. Augmented reality based instruction group showed higher learning flow than textbook based instruction group.

64 Bit EISC Processor Design (64 Bit EISC 프로세서 설계)

  • 임종윤;이근택
    • Proceedings of the IEEK Conference
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    • 2000.06b
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    • pp.161-164
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    • 2000
  • The architecture of microprocessor for a embedded system should be one that can perform more tasks with fewer instruction codes. The machine codes that high-level language compiler produces are mainly composed of specific ones, and codes that have small size are more frequently used. Extended Instruction Set Architecture (EISC) was proposed for that reason. We have designed pipe-line system for 64 bit EISC microprocessor. function level simulator was made for verification of design and instruction set architecture was also verified by that simulator. The behavioral function of synthesized logic was verified by comparison with the results of cycle-based simulator.

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Preceding Instruction Decoding Module(PIDM) for Test Performance Enhancement of JTAG based Systems (JTAG 기반 테스트의 성능향상을 위한 PIDM(Preceding Instruction Decoding Module)

  • 윤연상;김승열;권순열;박진섭;김용대;유영갑
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.8
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    • pp.85-92
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    • 2004
  • A design of a preceding instruction decoding module(PIDM) is proposed aiming at performance enhancement of JTAG-based test complying to the IEEE 1149.1 standard. The PIDM minimizes the number of clocks by performing test access port(TAP) instruction decoding process prior to the execution of TAP-controlled test activities. The scheme allows the generation of signals such as test mode select(TMS) inside of a target system. The design employing PIDM demonstrates 15% performance enhancement with simulation of a CORDIC processor and 48% reduction of the TAP-controller's circuit size with respect to the conventional design of a non-PIDM version.

A Study of an Instructional Design Strategy for Improving the Collaborative Teaching Between School Librarians and Subject Teachers in Library-Assisted Instruction (도서관 활용수업에서 사서교사와 교과교사의 협동수업 향상을 위한 교수설계 전략에 대한 연구)

  • Song, Gi-Ho
    • Journal of the Korean BIBLIA Society for library and Information Science
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    • v.21 no.2
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    • pp.111-127
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    • 2010
  • This study aims for developing an instructional design strategy to improve collaborative teaching between teacher librarians and subject teachers in library-assisted instruction. Collaborative teaching is an important management activity enhancing teaching role of teacher librarians in their school community. But in the actual condition the level of the library-assisted instruction as its practical strategy is cooperation and subject teachers are leading teaching and learning except for selecting resources. Because library-assisted instruction is resource-based learning, the procedural knowledge of information literacy curricula and topics of subject specific curricula should be designed as a whole. Also, there must be possibilities of reducing trial and error and expanding successes. From these sides, the collaborative design strategy for library-assisted instruction can be planned like 'statement of learning situation-co designing-co teaching-co evaluating'.