• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.12
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• pp.127-135
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• 2009

In this paper, the Interleaved AC/DC boost converter using two inductor with voltage-doubler characteristic when it operates with a duty cycle greater than 0.5 is proposed. Generally, the low-line(Input AC 110[V]) operation of the AC/DC boost converter is much less efficient than high-line (Input AC 220[V]) operation. The proposed Interleaved AC/DC boost converter operates as a voltage doubler at low-line. Its low-line range have higher power factor and improved efficiency compared with that of conventional converter. This research proposed the Interleaved AC/DC boost converter for voltage-doubler characteristic. The principle of operation, feature and design considerations is illustrated and the validity of verified through the experiment with a 300[W] based experimental circuit.

• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.172-178
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• 2019

This paper has designed, fabricated, and analyzed the passive devices realized using low temperature co-fired ceramic (LTCC) multi layer substrates by dividing into the shrinkage process and the non-shrinkage process. Using two types of ceramic materials with dielectric constant 7 or 40, we have fabricated the same shape of various elements in 2 different processes and compared the characteristics. For the substrate of dielctric constant 40, compared with the shrinkage process which has 17% shrink in the X and Y directions with 36% shrink in the Z direction, the non-shrinkage process has 43% shrink in the Z direction without shrink in the X and Y directions, so high dimensional accuracy and surface flatness can be obtained. The inductances and capacitances of the fabricated elements are estimated from measurement using empirical analysis equations of parameters and implemented as a design library. Depending on the substrate and the process, the inductance and capacitance depending on the turn number of winding and unit area have been measured, and empirical polynomials are proposed to predict element values.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.12
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• pp.1069-1077
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• 2011

In this paper, a design and fabrication of a miniaturized 2.5 GHz 8 W power amplifier using selectively anodized aluminum oxide(SAAO) substrate are presented. The process of SAAO substrate is recently proposed and patented by Wavenics Inc. which uses aluminum as wafer. The selected active device is a commercially available GaN HEMT chip of TriQuint company, which is recently released. The optimum impedances for power amplifier design were extracted using the custom tuning jig composed of tunable passive components. The class-F power amplifier are designed based on EM co-simulation of impedance matching circuit. The matching circuit is realized in SAAO substrate. For integration and matching in the small package module, spiral inductors and single layer capacitors are used. The fabricated power amplifier with $4.4{\times}4.4\;mm^2$ shows the efficiency above 40 % and harmonic suppression above 30 dBc for the second(2nd) and the third(3rd) harmonic at the output power of 8 W.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.6
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• pp.239-245
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• 2016

In this study, a 12 V PWM boost converter was designed with the optimal values of the external components of the power stage was well as the compensation stage for smart electronic applications powered by a battery device. The 12 V boost PWM converter consisted of several passive elements, such as a resistor, inductor and capacitor with a diode, power MOS switch and control IC chip for the control PWM signal. The devices of the power stage and compensation stage were designed to maintain stable operation under a range of load conditions as well as achieving the highest power efficiency. The results of this study were first verified by a simulation in SPICE from calculations of the values of major external elements comprising the converter. The design was also implemented on the prototype PCBboard using commercial IC LM3481 from Texas Instruments, which has a nominal output voltage of 12 V. The output voltage, ripple voltage, and load regulation with the line regulation were measured using a digital oscilloscope, DMM tester, and DC power supply. By configuring the converter under the same conditions as in the circuit simulation, the experimental results matched the simulation results.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.6
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• pp.57-65
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• 2007

This paper presents the design of single phase PFC(Power Factor Correction) using a DSP(TMS320F2812). In order to realize the proposed boost PFC converter in average current mode control, the DSP requires the A/D sampling values for a line input voltage, a inductor current, and the output voltage of the converter. Because of a FET switching noise, these sampling values contain a high frequency noise and switching ripple. The solution of A/D sampling keeps away from the switching point. Because the PWM duty is changed from 5% to 95%, we can#t decide a fixed sampling time. In this paper, the three A/D converters of the DSP are started using the prediction algorithm for the FET ON/OFF time at every sampling cycle(40 KHz). Implemented A/D sampling algorithm with only one timer of the DSP is very simple and gives the autostart of these A/D converters. From the experimental result, it was shown that the power factor was about 0.99 at wide input voltage, and the output ripple voltage was smaller than 5 Vpp at 80 Vdc output. Finally the parameters and gains of PI controllers are controlled by serial communication with Windows Xp based PC. Also it was shown that the implemented PFC converter can achieve the feasibility and the usefulness.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.2
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• pp.121-128
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• 2010

This paper presents a design of a 100 W high-efficiency power amplifier, whose operational frequency band expands from 30 to 512 MHz, using negative feedback network, push-pull structure, broadband RF choke, and transmission line transformer for balun configuration. The push-pull amplifier has been tuned for higher output power using a shunt capacitor as a matching component at its load especially for high-frequency region. The implemented power amplifier exhibited a very flat power gain of $18.34{\pm}0.9\;dB$ throughout the operating frequency band and very high power-added efficiency(PAE) of greater than 40% at an output power of 100 W. It also showed second- and third-harmonic distortion levels of below -34 dBc and -12 dBc, respectively, through the entire operating frequency band.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.21-26
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• 2016

This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.1
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• pp.114-124
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• 2011

In this paper, we present a 2 GHz compact analog phase shifter with linear phase-tune characteristic. The compact phase shifter was designed base on a lumped all pass network and implemented using a ceramic substrate fabricated with thin-film technique. For a linear phase-tune characteristic, a capacitance of the varactor diode for a tuning voltage was linearized by connecting series capacitor and subsequently produced an almost linear capacitance change. The inductor and bias circuit in the all pass network was implemented using a spiral inductors for small size, which results in the size reduction to $4\;mm{\times}4\;mm$. In order to measure the phase shifter using the probe station, two CPW pads are included at the input and output. The fabricated phase shifter showed an insertion loss of about 4.2~4.7 dB at 2 GHz band and a total $79^{\circ}$ phase change for DC control voltage from 0 to 5 V, and showed linear phase-tune characteristic as expected in the design.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.12 s.103
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• pp.1179-1185
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• 2005

In this paper, novel internal antenna with its controllable resonant frequency is presented for triple-band or over mobile handsets. The operating range can include GSM(880${\~}$960 MHz), GPS(1,575$\pm$10 MHz), DCS(1,710${\~}$1,880 MHz), US-PCS(1,850${\~}$l,990 MHz), and W-CDMA(1,920${\~}$2,170 MHz). The proposed antenna is realized by combination of a half wavelength loaded line and a shorted monopole. A single shorting and feeding points are used and they are common to both antenna structures. By controlling a value of lumped inductance element between shorting point and ground plane, the antenna provides enough bandwidth to cover DCS, US-PCS, and W-CDMA respectively. When these higher bands are controlled by the values of inductance, resonant characteristics in GSM and GPS bands are maintained. In this work, maximum value of the inductor is limited within 3.3 nH to mitigate gain degradation from frequency tuning. As a result, measured maximum gain of antenna is -0.58${\~}$-0.30 dBi in the GSM band, -0.57${\~}$0.43 dBi in the GPS band and 0.38${\~}$1.15 dBi in the DCS/US-PCS/W-CDMA band. In higher band, the proposed antenna is certified that resonant frequency of about 240 MHz can be effectively controlled within gain variation of about 0.77 dB by simulation and measurement.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.5
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• pp.197-203
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• 2016

In this paper, the dipole antenna that can control a beam steering were designed for attaching on LEO(Low Earth Orbit) small satellite. The proposed antenna was based on Yagi-Uda antenna. The parasitic element was proposed as a T-shape. Depending on the state of open or short at the end of a vertical element, we can choose a characteristic of the parasitic element with fixing a vertical element length of the parasitic element. Using this characteristic, we designed the director element and reflector element. The proposed antenna was designed to receive UHF 436.5 MHz. Antenna gain was chosen by link budget between one satellite and the other satellite or between the satellite and the ground station. By changing a vertical element length which is the largest variable that chooses an antenna characteristic, we confirmed that ${\lambda}/2$ length transformer has a result that improve 0.5 dB in comparison ${\lambda}/4$ length transformer from maximum gain direction. In production, we made an on/off switch composed of a diode, capacitor, and inductor control an open and short at the end of the parasitic element. As a result, the gain of antenna used in a link between one satellite and the other satellite had average 5.92 dBi. And the gain of antenna used in a link between the satellite and the ground station had average 0.99 dBi.