• Journal of information and communication convergence engineering
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• v.11 no.1
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• pp.50-55
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• 2013

In this paper, we propose a parallel intra-operation unit and a memory architecture for improving the performance of intra-prediction, which utilizes spatial correlation in an image to predict the blocks and contains 17 prediction modes in total. The design is targeted for portable devices applying H.264/AVC decoders. For boosting the performance of the proposed design, we adopt a parallel intra-operation unit that can achieve the prediction of 16 neighboring pixels at the same time. In the best case, it can achieve the computation of one luma $16{\times}16$ block within 16 cycles. For one luma $4{\times}4$ block, a mere one cycle is needed to finish the process of computation. Compared with the previous designs, the average cycle reduction rate is 78.01%, and the gate count is slightly reduced. The design is synthesized with the MagnaChip $0.18{mu}m$ library and can run at 125 MHz.

• The Transactions of the Korea Information Processing Society
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• v.5 no.8
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• pp.2050-2060
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• 1998

Weighting strategy is one of the necessary control strategies in automated reasoning to solve problecs within allowable time and computer memory. But, the strategy still consumes too much time since it depends soly on the user's experience and needs much of the user's manual work at each stage. This research suggests a tool which automates the weighting system to generate the weighting thesaurus and merges it to the mechanical theorem prover.

• Journal of Sensor Science and Technology
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• v.30 no.4
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• pp.223-228
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• 2021

This work presents a low-power CMOS image sensor (CIS) with a multi-column-parallel (MCP) readout structure while focusing on improving its performance compared to previous works. A delta readout scheme that utilizes the image characteristics is optimized for the MCP readout structure. By simply alternating the MCP readout direction for each row selection, additional memory for the row-to-row delta readout is not required, resulting in a reduced area of occupation compared to the previous work. In addition, the bias current of a pre-amplifier in a successive approximate register (SAR) analog-to-digital converter (ADC) changes according to the operating period to improve the power efficiency. The prototype CIS chip was fabricated using a 0.18-㎛ CMOS process. A 160 × 120 pixel array with 4.4 ㎛ pitch was implemented with a 10-bit SAR ADC. The prototype CIS demonstrated a frame rate of 120 fps with a total power consumption of 1.92 mW.

• International Journal of Internet, Broadcasting and Communication
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• v.15 no.1
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• pp.157-163
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• 2023

Recently, as businesses and data types become more complex and diverse, efficient data analysis using machine learning is required. However, since communication in the cloud environment is greatly affected by network latency, data analysis is not smooth if information delay occurs. In this paper, SPT (Safe Proper Time) was applied to the cluster-based machine learning data analysis agent proposed in previous studies to solve this delay problem. SPT is a method of remotely and directly accessing memory to a cluster that processes data between layers, effectively improving data transfer speed and ensuring timeliness and reliability of data transfer.

• Journal of Information Processing Systems
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• v.18 no.3
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• pp.332-343
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• 2022

To address the problems of the gravitational search algorithm (GSA) in which the population is prone to converge prematurely and fall into the local solution when solving the single-objective optimization problem, a sine map jumping gravity search algorithm based on asynchronous learning is proposed. First, a learning mechanism is introduced into the GSA. The agents keep learning from the excellent agents of the population while they are evolving, thus maintaining the memory and sharing of evolution information, addressing the algorithm's shortcoming in evolution that particle information depends on the current position information only, improving the diversity of the population, and avoiding premature convergence. Second, the sine function is used to map the change of the particle velocity into the position probability to improve the convergence accuracy. Third, the Levy flight strategy is introduced to prevent particles from falling into the local optimization. Finally, the proposed algorithm and other intelligent algorithms are simulated on 18 benchmark functions. The simulation results show that the proposed algorithm achieved improved the better performance.

• Proceedings of the Korea Information Processing Society Conference
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• 2023.05a
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• pp.525-526
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• 2023

최근 빅데이터를 처리하기 위한 고용량의 저장장치의 연구가 활발하게 진행되고 있다. 특히 낸드 플래시 메모리 기반 저장장치인 SSD(Solid State Drive)는 고속 데이터 처리가 가능하기 때문에 다양한 저장 시스템에서 사용되고 있다. 그러나 낸드 플래시 메모리는 읽기 속도가 빠르고 쓰기 속도가 느린 비대칭 구조를 가지고 있어 데이터 쓰기 작업이 진행 중일 때 다른 작업이 대기하게 되어 전체적인 시스템 성능에 영향을 미칠 수 있다. 이에 대해 대부분의 연구에서는 쓰기 성능을 개선하기 위한 버퍼 관리 정책들이 제안되었다. 기술의 발전으로 쓰기 성능은 개선되었지만, 그에 비해 읽기 성능이 저조한 문제가 있다. 본 논문에서는 읽기 성능이 쓰기 성능보다 취약한 점을 분석하고 플래시 메모리 내에 저장장치 속도를 개선하기 위해 앞으로 읽기 요청 가능성이 있는 예상 데이터를 선형회귀 모델을 적용하여 전송 대기 시간 중 미리 읽는 정책을 제안한다.

• Journal of Practical Engineering Education
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• v.15 no.2
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• pp.485-494
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• 2023

The purpose of this study was to examine the relationship between writing self-efficacy and academic achievement in a project-based university writing class, and the mediating effect of reflective journal writing. A total of 135 college students participated in the study. The results showed that students with higher writing self-efficacy had higher academic achievement and wrote more reflective journaling. Reflective journaling was found to have a positive impact on reviewing learned content, improving metacognition and memory, and promoting idea development. Overall, consistent reflective journal writing not only enhanced writing self-efficacy but also positively influenced academic performance.

• Electronics and Telecommunications Trends
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• v.39 no.3
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• pp.1-12
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• 2024

As the demand for high-performance semiconductors, such as chips for artificial intelligence and high-bandwidth memory devices, increases along with the limitations of ultrafine processing technology in the semiconductor in-line process, advanced packaging becomes an increasingly important breakthrough technology for further improving semiconductor performance. Major countries, including Korea, the United States, Taiwan, and China, and large companies are strengthening their technological industry capabilities through the development of advanced packaging technology and policy support. Nevertheless, Korea has a lower level of development of related technologies by approximately 66% compared with the most advanced countries. Therefore, we aim to discover the needs for an advanced packaging research and development (R&D) policy through written expert interviews and importance satisfaction analysis. As a result, various implications for R&D policy directions are suggested to strengthen the technological capabilities and R&D ecosystem of the Korean advanced packaging technology.

• Proceedings of the Korean Society of Computer Information Conference
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• 2024.01a
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• pp.229-230
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• 2024

본 논문에서는 키넥트 센서 기반의 치매 예방 애플리케이션을 설계하고 구현한다. 이 애플리케이션은 노년층의 치매 예방을 위해 기억력을 향상시키고 간단한 동작으로 운동을 촉진할 수 있는 햄버거 만들기 게임을 구현한다. 햄버거 만들기 게임은 키넥트 센서 기반으로 조인트와 스켈레톤 기능을 활용하여 하늘에서 떨어지는 재료들을 순서에 맞게 획득하여 햄버거를 완성함으로써 점수를 얻는다. 사용자들은 제한 시간이 끝날 때까지 계속 진행하며 순서를 기억해 내는 과정을 통해 기억력을 향상시키고, 재료를 잡기 위한 활동적인 움직임으로 치매 예방에 도움이 되는 운동 기능을 제공한다.

• ETRI Journal
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• v.46 no.3
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• pp.501-512
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• 2024

With an explosive increase of data produced annually, researchers have been attempting to develop solutions for systems that can effectively handle large amounts of data. Single-operating-system (OS) non-uniform memory access (NUMA) abstraction technology is an important technology that ensures the compatibility of single-node programming interfaces across multiple nodes owing to its higher cost efficiency compared with scale-up systems. However, existing technologies have not been successful in optimizing user performance. In this paper, we introduce a single-OS NUMA abstraction technology that ensures full compatibility with the existing OS while improving the performance at both hypervisor and guest levels. Benchmark results show that the proposed technique can improve performance by up to 4.74× on average in terms of execution time compared with the existing state-of-the-art opensource technology.