• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.163-170
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• 2007

In this paper, we propose that the polyphase scaler whose performance to that of the bicubic method, has less complexity in hardware structure. In order to get the new information, proposed system is based on the group delay which is one of the digital filter characteristics. The performance of this system is superior to that of bicubic algorithm which is well known. Because the hardware structure is simpler than other image scalers, we can adopt this system for mobile devices easily. The previous polyphase filters make blurring noise which is generated by up-scaling. We replace polyphase filters by boost-up filter to get vivid image. The proposed scaler is verified by Xilinx Virtex2 FPGA and is used as digital Boom in mobile camera phone.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.22-34
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• 2010

Existing image scalers generally adopt simple interpolation methods such as bilinear method to take cost-benefit, or highly complex architectures to achieve high quality resulting images. However, demands for a low power, low cost, and high performance image scaler become more important because of emerging high quality mobile contents. In this paper we propose the novel low power hardware architecture for a high quality raster scan image scaler. The proposed scaler architecture enhances the existing cubic interpolation look-up table architecture by reducing and optimizing memory access and hardware components. The input data buffer of existing image scaler is replaced with line memories to reduce the number of memory access that is critical to power consumption. The cubic interpolation formula used in existing look-up table architecture is also rearranged to reduce the number of the multipliers and look-up table size. Finally we analyze the optimized parameter sets of look-up table, which is a trade-off between quality of result image and hardware size.

• Journal of Broadcast Engineering
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• v.13 no.5
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• pp.707-718
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• 2008

We derive a modified version of the cubic convolution scaler to enlarge or reduce the size of digital image with arbitrary ratio. To enhance the edge information of the scaled image and to obtain a high-quality scaled image, the proposed scaler is applied along the direction of an edge. Since interpolation along the direction of an edge has to process nonuniformly sampled data, the kernel of the cubic convolution scaler is modified to interpolate the data. The proposed scaling scheme can be used to resize pictures in various formats in a transcoding system that transforms a bit stream compressed at one bit rate into one compressed at another bit rate. In many applications, such as transcoders, the resolution conversion is very important for changing the image size while maintaining high quality of the scaled image. We show experimental results that demonstrate the effectiveness of the proposed interpolation method. The proposed scheme provides clearer edges, without artifacts, in the resized image than do conventional schemes. The algorithm exhibits significant improvement in the minimization of information loss when compared with the conventional interpolation algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9C
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• pp.867-880
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• 2007

We derive a modified version of cubic convolution interpolation for the enlargement or reduction of digital images by arbitrary scaling factors. The proposed scaling scheme is used to resize various format pictures in the transcoding system, which transforms the bitstream compressed at a bit rate, such as the HD bitstream, into another bit rate stream. In many applications such as the transcoder, the resolution conversion is very important for changing the image size while the scaled image maintains high quality. We focus on the modification of the scaler kernel according to the relation between formats of the original and the resized image. In the modification, various formats defined in MPEG standards are considered. We show experimental results that demonstrate the effectiveness of the proposed interpolation method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.99-102
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• 2012

An image scaler is a IP used in a image processing block of display devices to adjust image size. Proposed image scaler adopts line memories instead of a conventional method using a frame memory. This method reduced hardware resources and enhanced data precision by using shift operations that number is multiplied by $2^m$ and divided again at final stage for scaling. Also image scaler increased efficiency of IP by using serial divider to calculate parameters by itself. Parameters used in image scaling is automatically produced by it. Suggested methods are designed by Verilog HDL and implemented with Xilinx Vertex-4 XC4LX80 and ASIC using TSMC 0.18um process.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2013.06a
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• pp.296-299
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• 2013

디스플레이 기술이 발전함에 따라 다양한 크기의 디스플레이를 탑재한 장치들이 등장하게 되었고, 다양한 디스플레이 크기만큼 다양한 해상도를 사용하고 있다. 때문에 비디오 코덱과 scaler는 보편적으로 함께 사용된다. 그러나 기존의 scaler는 비디오 코덱의 복호화기와 화면 해상도 변환 모듈이 독립적으로 구성되고, 서로 간에 정보를 이용하지 않으므로 시스템의 성능 개선에 한계가 존재하였다. 즉, 비디오 코덱의 복호화기는 비트스트림으로부터 복호한 정보를 바탕으로 영상을 복원하고, 복원영상은 up/down scaler에서 확대/축소를 수행한다. 하지만 비디오 코덱의 비트스트림에 존재하는 정보는 영상의 특성을 반영하기 때문에 up/down scaler에서 비디오 코덱의 복호화기에서 복호된 정보를 이용하면 복잡도의 증가 없이 효율적인 확대/축소를 수행할 수 있다. 이에 본 논문에서는 비디오 코덱 중 차세대 비디오 코덱인 H.264/AVC 복호화기에서 생성된 복원 영상에 대해서 별도로 영상의 특성을 계산하는 모듈 없이 H.264/AVC 복호화기에서 복원된 정보 중 인트라 모드 정보를 바탕으로 영상의 특성에 맞는 up/down scaler를 구현하는 방법을 제안한다. 이 방법은 기존의 scaler들보다 물체의 경계영역을 더 선명하게 확대하는 효과를 보인다.

• 한국HCI학회:학술대회논문집
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• 2009.02a
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• pp.615-619
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• 2009

A real-time, continuous-scale image interpolation method is proposed based on bi-linear interpolation with directionally adaptive low-pass filtering. The proposed algorithm has been optimized for hardware implementation. The original bi-linear interpolation method has blocking artifact. The proposed algorithm solves this problem using directionally adaptive low-pass filtering. It can also solve the severely problem by selection choosing low-pass filter coefficients. Therefore the proposed interpolation algorithm can realize a high-quality image scaler for various imaging systems, such as digital camera, CCTV and digital flat panel display, to name a few.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.3
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• pp.93-101
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• 2001

In this paper, we propose an image downscaler used in multimedia video applications, such as DTV, TV-PIP, PC-video, camcorder, videophone and so on. The proposed image downscaler provides a scaled image of high-quality and high-performance. This paper will explain the scaling theory using two-dimensional digital filters. It is the method that removes an aliasing noise and decreases the hardware complexity, compared with Pixel-drop and Upsamling. Also, this paper will prove it improves scaling precisians and decreases the loss of data, compared with the Scaler32, the Bt829 of Brooktree, and the SAA7114H of Philips. The proposed downscaler consists of the following four blocks: line memory, vertical scaler, horizontal scaler, and FIFO memory. In order to reduce the hardware complexity, the using digital filters are implemented by the multiplexer-adder type scheme and their all the coefficients can be simply implemented by using shifters and adders. It also decreases the loss of high frequency data because it provides the wider BW of 6MHz as adding the compensation filter. The proposed downscaler is modeled by using the Verilog-HDL and the model is verified by using the Cadence simulator. After the verification is done, the model is synthesized into gates by using the Synopsys. The synthesized downscaler is Placed and routed by the Mentor with the IDEC-C632 0.65${\mu}{\textrm}{m}$ library for further IC implementation. The IC master is fixed in size by 4,500${\mu}{\textrm}{m}$$\times$4,500${\mu}{\textrm}{m}$. The active layout size of the proposed downscaler is 2,528${\mu}{\textrm}{m}$$\times$3,237${\mu}{\textrm}{m}$.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.3
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• pp.128-134
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• 2014

A real-time, continuous-scale image interpolation method is proposed based on a bilinear interpolation with directionally adaptive low-pass filtering. The proposed algorithm was optimized for hardware implementation. The ordinary bi-linear interpolation method has blocking artifacts. The proposed algorithm solves this problem using directionally adaptive low-pass filtering. The algorithm can also solve the severe blurring problem by selectively choosing low-pass filter coefficients. Therefore, the proposed interpolation algorithm can realize a high-quality image scaler for a range of imaging systems, such as digital cameras, CCTV and digital flat panel displays.

• Journal of IKEEE
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• v.27 no.3
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• pp.296-302
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• 2023

As Multimedia industry has evolved, it has become possible to display resolutions in various formats. Therefore, the performance of a scaler algorithm that converts resolutions while maintaining high quality and its hardware implementation are important. Considering the hardware design of an image up/down scaler, this paper proposes a combinatorial scaler algorithm that uses modified bilinear interpolation in the vertical direction and bicubic interpolation in the horizontal direction to reduce the line memory burden. Through quantitative and qualitative evaluations, this paper compared the performance of the proposed algorithm with three other well-known algorithms, and also compared the hardware burden of its hardware implementation. This paper used a sinusoidal signal and eight typical images for performance evaluation.