• Steel and Composite Structures
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• v.25 no.6
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• pp.639-648
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• 2017

Fracture energy values KV have been measured on cast steel, used in the container manufacture, by instrumented Charpy impact testing. This material has a large ductility on the upper transition region at $+20^{\circ}C$ and a ductile tearing with an expended plasticity before a brittle fracture on the lower transition region at $-20^{\circ}C$. To assess the fracture toughness of this material we use, the $K_{IC}$-KV correlations to measure the critical stress intensity factor $K_{IC}$ on the lower transition region and the dynamic force - displacement curves to measure the critical fracture toughness $J{\rho}_C$, the essential work of fracture ${\Gamma}_e$ on the upper transition region. It is found, using the $K_{IC}$-KV correlations, that the critical stress intensity factor $K_{IC}$ remains significant, on the lower transition region, which indicating that our testing material preserves his ductility at low temperature and it is apt to be used as a container's material. It is, also, found that the $J_{\rho}-{\rho}$ energetic criterion, used on the upper transition region, gives a good evaluation of the fracture toughness closest to those found in the literature. Finally, we show, by using the ${\Gamma}_e-K_{IC}$ relation, on the lower transition region, that the essential work of fracture is not suitable for the toughness measurement because the strong scatter of the experimental data. To complete this study by a numerical approach we used the ANSYS code to determine the critical fracture toughness $J_{ANSYS}$ on the upper transition region.

• Progress in Superconductivity and Cryogenics
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• v.10 no.1
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• pp.28-31
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• 2008

22.9kV 50MVA HTS power cable has been developed and tested by Korea Electrotechnology Research Institute and LS Cable Company and it was supported by a grant from Center for Applied Superconductivity Technology of the 21st Century Frontier R&D Program. In this paper, DC Ic of 100m HTS cable which is installed at Kochang testing station was measured and analyzed. A measurement technique of DC Ic used by resistance and inductance removal method is established.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1069-1072
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• 1998

Recently the development of design and automation technology and manufacturing method, has reduced the cost of chip, but it becomes more difficult to test IC chip because test technique doesn't keep up with these techniques. In case of IC testing, obtaining test vectors to be able to detect good chip or bad one is very important, but according to increasing complexity, it is very complex and difficult. Another problem is that during testing, there could be capability of physical and electrical damage on chip. Also there is difficulty in synchronization between CUT (circuit under test) and Test equipment〔1〕. Because of these difficulties, built in self test has been proposed. Not only obtaining test vectors but also reducing test time becomes hot issues nowadays. This paper presents a new test BIST(built in self test) method. Proposed BIST implementation reduces test time and obtains high fault coverage. By searching internal nodes in which are inserted test_point_cells〔2〕and allocating TPG(test pattern generation) stages, test length becomes much shorter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.34-47
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• 2006

In this paper, a new testing technique for core components of wireless transceiver was proposed. That was, band fault models (including the information of specifications in the analogue and RF IC) and methods which can test specifications in the time domain easily by observing a variation of band fault models in the circuit output were proposed and developed. This technique had an advantage over testing technique in frequency domain because it didn't need expensive test equipments and could reduce the time required. Test technique proposed in this paper was adapted to the test of 5.25 GHz low noise amplifier and proved that this testing technique was efficient in RF IC including low noise amplifier.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.3_4
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• pp.160-169
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• 2004

With an emergence of SOC from developed IC technology, the VLSI design has required the core re-use technique and modular test development. To minimize the cost of testing SOC, an efficient method is required to optimize the test time and area overhead in conjunction for the core test wrapper, which is one of the important elements for SOC test architecture. In this paper, we propose an efficient design strategy of core test wrapper to achieve the minimum cost for SOC testing. The proposed strategy adopted advantages of traditional methods and more developed to be successfully used in practice.

• Journal of Advanced Engineering and Technology
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• v.5 no.4
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• pp.349-353
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• 2012

Recently, Mobile multimedia equipments as smart phone and tablet pc requirement is increasing and this market is also being expanded. These mobile equipments require large multi-media function, so more power consumption is required. For these reasons, the needs of power management IC as switching type dc-dc converter and linear regulator have increased. DC-DC buck converter become more important in power management IC because the operating voltage of VLSI system is very low comparing to lithium-ion battery voltage. There are many people to be concerned about digital DC-DC converter without using external passive device recently. Digital controlled DC-DC converter is essential in mobile application to various external circumstance. This paper proposes the DC-DC Buck Converter using the AVR RISC 8-bit micro-processor control. The designed converter receives the input DC 18-30 [V] and the output voltage of DC-DC Converter changes by the feedback circuit using the A/D conversion function. Duty ratio is adjusted to maintain a constant output voltage 12 [V]. Proposed converter using the micro-processor control was compared to a typical boost converter. As a result, the current loss in the proposed converter was reduced about 10.7%. Input voltage and output voltage can be displayed on the LCD display to see the status of the operation.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.11
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• pp.981-987
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• 2014

DC/DC switching power converters are commonly used to generate a regulated DC output voltage with high efficiency. The DC/DC converter is composed of a MOSFET (metal-oxide semiconductor field effect transistor), a PWM-IC (pulse width modulation-integrated circuit) controller, inductor, capacitor, etc. It is shown that the variation of threshold voltage and the breakdown voltage in the electrical characteristics of MOSFET occurs by radiation effects in TID (Total Ionizing Dose) testing at the low energy ${\gamma}$ rays using $^{60}Co$, and 5 heavy ions make the gate of MOSFET broken in SEGR (Single Event Gate Rupture) testing. TID testing on MOSFET is accomplished up to the total dose of 40 krad, and the cross section($cm^2$) versus LET(MeV/mg/$cm^2$) in the MOSFET operation is studied at SEGR testing after implementation of the controller board.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.11
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• pp.1164-1171
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• 2014

Bulk Current Injection(BCI) test is a method of injecting current into Integrated Circuit(IC) using a current injection probe to qualify the standards of Electromagnetic Compatibility(EMC). This paper, we propose a microstrip coupler structure that can replace the BCI current injection probe that is used to inject a RF noise in standard IEC 62132-part 3 documented by International Electrotechnical Commission. Conventional high cost BCI probe has mostly been used in testing automotive ICs that use high supply voltage. We propose a compact microstrip coupler which is suitable for immunity testing of low power ICs. We tested its validity to replace the BCI injection probe from 100 MHz to 1,000 MHz. We compared the power[dBm] that is needed to generate the same level of noise between current injection probe and microstrip coupler by sweeping the frequency. Results show that microstrip coupler can inject the same level of noise into ICs for immunity test with less power.

• Proceedings of the Acoustical Society of Korea Conference
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• 1987.11a
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• pp.48-51
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• 1987

In this paper, acoustic reflection microscope system has been built for the purpose of detecting subsurface defects in materials and demonstrated for nondestructive testing application. 100 won coin, aluminuim, ceramics, and IC component employed as experimental samples and acoustic reflection microscope was operated in the focused and defocused mode at a frequency of operation of 3 MHz. It has been found that acoustic reflection icroscope has the resolution of 500 ${\mu}{\textrm}{m}$ and it has been an excellent tool for nondestructive testing.

• Steel and Composite Structures
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• v.51 no.4
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• pp.351-361
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• 2024

Accurate measurement of K_IC values for gas pipeline steels is important for assessing pipe safety using failure assessment diagrams. As direct measurement of K_IC was impossible for the API X70 pipeline steel, multi-specimen fracture tests were conducted to measure J_IC using three-point bend geometry. The J values were calculated from load-displacement (F-δ) plots, and the associated crack extensions were measured from the fracture surface of test specimens. Valid data points were found for the constructed J-Δa plot resulting in J_IC=356kN/m. More data points were added analytically to the J-Δa plot to increase the number of data points without performing additional experiments for different J-Δa zones where test data was unavailable. Consequently, displacement (δ) and crack-growth (Δa) from multi-specimen tests (with small displacements) were used simultaneously, resulting in the variation of Δa-δ (crack growth law) and δ-Δa obtained for this steel. For new Δa values, corresponding δ values were first calculated from δ-Δa. Then, corresponding J values for the obtained δ values were calculated from the area under the F-δ record of a full-fractured specimen (with large displacement). Given Δa and J values for new data points, the developed J-Δa plot with extra data points yielded a satisfactory estimation of J_IC=345kN/m with only a -3.1% error. This is promising and showed that the developed technique could ease the estimation of J_IC significantly and reduce the time and cost of expensive extra fracture toughness tests.