Journal of KIISE:Computer Systems and Theory (한국정보과학회논문지:시스템및이론)

Korean Institute of Information Scientists and Engineers (한국정보과학회)
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An Efficient Design Strategy of Core Test Wrapper For SOC Testing

SOC 테스트를 위한 효율적인 코어 테스트 Wrapper 설계 기법

  • 김문준 (숭실대학교 컴퓨터학과) ;
  • 장훈 (숭실대학교 컴퓨터학과)
  • Published : 2004.04.01
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Abstract

With an emergence of SOC from developed IC technology, the VLSI design has required the core re-use technique and modular test development. To minimize the cost of testing SOC, an efficient method is required to optimize the test time and area overhead in conjunction for the core test wrapper, which is one of the important elements for SOC test architecture. In this paper, we propose an efficient design strategy of core test wrapper to achieve the minimum cost for SOC testing. The proposed strategy adopted advantages of traditional methods and more developed to be successfully used in practice.

IC 집적기술이 고도로 발달하면서 출현한 SOC(System On a Chip)는 미리 설계된 코어를 재 사용하는 모듈러 기법을 회로 설계 과정에 도입시켰고, 따라서 테스트 설계에도 모듈러 기법이 도입되었다. 이러한 SOC 테스트에 소요되는 비용의 최소화를 위해서는, SOC 테스트 구조의 핵심 구성요소인 코어 테스트 wrapper의 테스트 시간과 테스트 면적을 동시에 최적화시킬 수 있는 설계 기법이 필요하다. 본 논문에서는 최소 비용의 SOC 테스트를 위한 효율적인 코어 테스트 Wrapper 설계 기법을 제안한다. 본 논문에서 제안하는 기법은 기존의 기법들이 각기 가지고 있는 장점들을 하나로 취합하고 더욱 발전시킴으로써 필드에서 실재적으로 사용될 수 있는 효율적인 코어 테스트 wrapper 설계 기법이다.

Keywords

References

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