1 |
J. Dabrowski, 'Fault Modeling of RF Blocks Based on Noise Analysis', ISCAS 2004, pp.513-516, 2004
DOI
|
2 |
R. Kheriji, V. Danelon, J. L. Carbonero and S. Mir, 'Optimizing Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach', DATE'05, vol.1, pp.170-171, 2005
DOI
|
3 |
S. Bhattacharya, A. Halder and A. Chatterjee, 'Automatic Multitone Alternate Test Generation for RF Circuits Using Behavioral Models', International Test Conference, pp.665-673, 2003
DOI
|
4 |
B. Atzema and T. Zwemstra, 'Exploit Analog IFA to Improve Specification Based Tests', Proceedings of European Design and Test Conference, pp.542-546, 1996
DOI
|
5 |
S. D. Huss, R. S. Gyurcsic, and J. J. Paulos, 'Optimal Ordering of Analog Integrated Circuit Tests to Minimize Test Time,' Proceedings of Design Automation Conference, pp.494-499, 1991
|
6 |
A. Balivada, J. Chen and J. A. Abraham, 'Analog Testing with Time Response Parameters,' IEEE Design and Test of Computers, pp.18-25, vol.13, 1996
DOI
ScienceOn
|
7 |
M. Slamani and B. Kaminska, 'Multifrequency Analysis of Faults in Analog Circuits,' IEEE Design and Test of Computers, vol.12, no.2, pp.70-80, 1995
DOI
ScienceOn
|
8 |
R. Kondagunturi, E. Bladley, K. Maggard and C. Stroud, 'Benchmark Circuits for Analog and Mixed-Signal Testing,' Southeastcon' 99, Proceedings, IEEE 25-28, pp.217-220, March, 1999
DOI
|
9 |
Cadence SpectreRF user guide
|
10 |
Q. Wang, Y. Tang and M. Soma, 'GHz RF Front-end Bandwidth Time Domain Measurement', IEEE VLSI Test Symposium, pp. 223-228, 2004
DOI
|
11 |
P. N. Variyam and A. Chatterjee,' Test Generation for Comprehensive Testing of Linear Analog Circuits Using Transient Response Sampling,' Int. Conference on Computer Aided Design, pp.382- 385, 1997
DOI
|
12 |
S. J. Chang and C.L. Lee, 'Structural Fault Based Specification Reduction for Testing Analog Circuits,' Journal of Electronic Testing: Theory and Application 18, pp. 571-581, 2002
DOI
ScienceOn
|
13 |
C. Yu, J. S. Yuan and H. Yang, 'MOSFET Linearity Performance Degradation Subject to Drain and Gate Voltage Stress', IEEE Transactions on Device and Materials Reliability, vol.4, pp.681-689, Dec. 2004
DOI
ScienceOn
|
14 |
S. G. Lee and R. D. Schultz, 'Production DC Screening for RF Performance of A 900 MHz Monolithic Low Noise Amplifier', IEEE Microwave and Millimeter-Wave Monolithic Circuits Symposium, pp.69-72, 1995
DOI
|
15 |
P. N. Variyam and A. Chatterjee, 'Enhancing Test Effectiveness for Analog Circuits Using Synthesized Measurements', Proc. VLSI Test Symposium, pp.132-137, 1998
DOI
|
16 |
L. Milor and A. S. Vincentelli, 'Minimizing Production Test Time to Detect Faults in Analog Integrated Circuits', IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.13, no.6, pp.796-813, June, 1994
DOI
ScienceOn
|
17 |
H. H. Zheng, A. Balivada and J. A. Abraham, 'A Novel Test Generation Approach for Parametric Faults in Linear Analog Circuits', VLSI Test Symposium, pp.470-475, 1996
DOI
|
18 |
P. N. Variyam, A. Chatterjee and N. Nagi, 'Low-Cost and Efficient Digital-Compatible BIST for Analog Circuits Using Pulse Response Sampling,' 15th IEEE VLSI Test Symposium,pp.261-266, 1997
DOI
|
19 |
J. Gyvez, G. Gronthoud and R. Amine, 'VDD Ramping Testing for RF Circuits,' Int. Test Conference'03, pp.651-658, 2003
DOI
|
20 |
J. Dabrowski, 'BiST Model for IC RF-Transceiver Front-End', Proceeding of Design for Testability'03, pp.295-302, 2003
|
21 |
R. Voorakaranam, S. Cherubal and A. Chatterjee, 'A Signature Test Framework for Rapid Production Test of RF Circuits', Proceedings of Design Automation and Test in Europe, pp.186-191, 2002
DOI
|