• Title/Summary/Keyword: IC circuit

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Design of Planar Power Divider Combiner for K-Band and Improvement of Impedence Matching Condition (K-밴드 평면형 Power Divider / Combiner와 정합특성에 관한 연구)

  • 나극환;홍의석;강준길;김춘길
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.14 no.6
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    • pp.579-589
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    • 1989
  • In this paper, planar power dividers/combiners for millimeter waves K-band or bands which can be printed on the substrates of hybrid or monolithic IC by surface mounting are designed and studied. Power dividers/combiners, and the conductor loss of microstrip lines in particualr the existing Wilkinson power dividers/combiners is modified ad amployes by ist equivalent circuit. Microwave CAD program SUPEROMPACT is employed for the Wilkinson power combiner which is modified and analyzed to reduce the high frequency coupling between the branches of the combiner, and the method to diminish the sensitivity of the input reflection of $2^n$-way power dividers/combiners is studied employing the commerical microwave CAD program package SUPERCOMPACT.

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Laser Micro-drilling of Sapphire/silicon Wafer using Nano-second Pulsed Laser (나노초 펄스 레이저 응용 사파이어/실리콘 웨이퍼 미세 드릴링)

  • Kim, Nam-Sung;Chung, Young-Dae;Seong, Chun-Yah
    • Journal of the Korean Society for Precision Engineering
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    • v.27 no.2
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    • pp.13-19
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    • 2010
  • Due to the rapid spread of mobile handheld devices, industrial demands for micro-scale holes with a diameter of even smaller than $10{\mu}m$ in sapphire/silicon wafers have been increasing. Holes in sapphire wafers are for heat dissipation from LEDs; and those in silicon wafers for interlayer communication in three-dimensional integrated circuit (IC). We have developed a sapphire wafer driller equipped with a 532nm laser in which a cooling chuck is employed to minimize local heat accumulation in wafer. Through the optimization of process parameters (pulse energy, repetition rate, number of pulses), quality holes with a diameter of $30{\mu}m$ and a depth of $100{\mu}m$ can be drilled at a rate of 30holes/sec. We also have developed a silicon wafer driller equipped with a 355nm laser. It is able to drill quality through-holes of $15{\mu}m$ in diameter and $150{\mu}m$ in depth at a rate of 100holes/sec.

English Digital Signal Processing Circuit in HD Monitor using Synchronization Signal Optimization (동기신호 최적화 기법을 통한 고품위급 모니터의 디지털 신호처리회로 구현)

  • 천성렬;김익환;이호근;하영호
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.11C
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    • pp.1152-1160
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    • 2003
  • Start The current paper proposes an improved HD(High Definition) monitor that can support a signal input with various resolutions. Due to the inadequate performance of the built-in digital PLL(Phase-locked Loop) of an ADC(Analog to Digital Converter) and poor tolerance of ADC ICs, there are problems in the stable processing of synchronization signals with various input signals. Accordingly, the proposed synchronization signal optimization technique regenerates the horizontal synchronization signal in the vertical blanking interval based on the regularity of the synchronization signal, i.e. the timing of the falling edge signal remains constant, thereby solving the above problem and minimizing the interference of the system. As a result, the proposed system can stabilize various synchronization signals with different resolution modes.

Current and Future Trends of Smart Card Technology (스마트카드형 교통 카드의 기술 및 미래 동향)

  • Lee, Jung-Joo;Shon, Jung-Chul;Yu, Sin-Cheol
    • Proceedings of the KSR Conference
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    • 2008.06a
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    • pp.535-544
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    • 2008
  • Unlike MS(Magnetic Stripe), SMART CARD is equipped with COS(Chip Operating System) consisting of the Microprocessor and Memory where information can be stored and processed, and there are two types of cards according to the contact mode; the contact type that passes through a gold plated area and the contactless one that goes through the radio-frequency using an antenna embedded in the plastic card. the contactless IC card used for the transportation card was first introduced into local area buses in Seoul, and expanded throughout the country so that it has removed the inconvenience such as possession of cash, fare payment and collection. Focusing on the Seoul metropolitan area in 2004, prepaid and pay later cards were adopted and have been used interchangeably between a bus and subway. The card terminal compatible between a bus and subway is Proximity Integrated Circuit Card(PICC) as international standards(1443 Type A,B), communicates in the 13.56MHz dynamic frequency modulation-demodulation system, and adopts the Multi Secure Application Module(SAM). In the second half of 2009, the system avaliable nationwide will be built when the payment SAM standard is implemented.

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AlN Based RF MEMS Tunable Capacitor with Air-Suspended Electrode with Two Stages

  • Cheon, Seong J.;Jang, Woo J.;Park, Hyeon S.;Yoon, Min K.;Park, Jae Y.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.1
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    • pp.15-21
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    • 2013
  • In this paper, a MEMS tunable capacitor was successfully designed and fabricated using an aluminum nitride film and a gold suspended membrane with two air gap structure for commercial RF applications. Unlike conventional two-parallel-plate tunable capacitors, the proposed tunable capacitor consists of one air suspended top electrode and two fixed bottom electrodes. One fixed and the top movable electrodes form a variable capacitor, while the other one provides necessary electrostatic actuation. The fabricated tunable capacitor exhibited a capacitance tuning range of 375% at 2 GHz, exceeding the theoretical limit of conventional two-parallel-plate tunable capacitors. In case of the contact state, the maximal quality factor was approximately 25 at 1.5 GHz. The developed fabrication process is also compatible with the existing standard IC (integrated circuit) technology, which makes it suitable for on chip intelligent transceivers and radios.

Selection of target for the minimum expected loss in plating processes (도금공정에서 최소기대손실을 위한 목표치의 설정)

  • Park, Chang-soon;Kim, Jung-Jun
    • Journal of the Korean Data and Information Science Society
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    • v.21 no.6
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    • pp.1051-1060
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    • 2010
  • In the plating process of the IC chips for the printed circuit board manufacturing, specification limits for the plating thickness are usually given but its target is not specified in most cases. When the target is not specified, the center point of the specification limits is used instead. When the process capability is large, however, the use of the center point for the target is not the best choice in the context of the total cost. In this paper, the total cost is defined in terms of the production cost and the loss function, and then the optimal choice for target is studied in order to minimize the expected loss. As a consequence, the optimal choice of the target reduces the expected loss significantly, while reducing the process capability slightly.

A Study on the Per-Channel CPCM Method by means of the 1-Bit Interpolation (1-Bit Interpolation을 이용한 Per-Channel CPCM부호화방식에 관한 연구)

  • 정해원;조성준
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.7 no.2
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    • pp.47-54
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    • 1982
  • In this paper, a improved per-channel PCM Coder with 1-bit interpolation is proposed. The coder converts a telephone signal to 15-segments u-law PCM signal of a large dynamic range. The A/D conversion technique of the proposed converter requires a feedback loop around a quantizer operates at high speed, and a accumulater for accumulating the quantized values to provide PCM outputs. To obtain both linear and compressed PCM signals a improved table look-up method is presented. The operations of the proposed converter are certified through the experiments to be good. The experimental circuit comprises TTL logic gates, a resistive D/Z converter and a simple differential amplifier. From the results of the experiments, it is known that the proposed converter has many advantage to be adopted economically for per-channel onverter used in rural area service.

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Clock Mesh Network Design with Through-Silicon Vias in 3D Integrated Circuits

  • Cho, Kyungin;Jang, Cheoljon;Chong, Jong-Wha
    • ETRI Journal
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    • v.36 no.6
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    • pp.931-941
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    • 2014
  • Many methodologies for clock mesh networks have been introduced for two-dimensional integrated circuit clock distribution networks, such as methods to reduce the total wirelength for power consumption and to reduce the clock skew variation through consideration of buffer placement and sizing. In this paper, we present a methodology for clock mesh to reduce both the clock skew and the total wirelength in three-dimensional integrated circuits. To reduce the total wirelength, we construct a smaller mesh size on a die where the clock source is not directly connected. We also insert through-silicon vias (TSVs) to distribute the clock signal using an effective clock TSV insertion algorithm, which can reduce the total wirelength on each die. The results of our proposed methods show that the total wirelength was reduced by 12.2%, the clock skew by 16.11%, and the clock skew variation by 11.74%, on average. These advantages are possible through increasing the buffer area by 2.49% on the benchmark circuits.

A Small Scaling Lateral Trench IGBT with Improved Electrical Characteristics for Smart Power IC

  • Moon, Seung Hyun;Kang, Ey Goo;Sung, Man Young
    • Transactions on Electrical and Electronic Materials
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    • v.2 no.4
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    • pp.15-18
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    • 2001
  • A new small scaling Lateral Trench Insulated Gate Bipolar Transistor (SSLTIGBT) was proposed to improve the characteristics of the device. The entire electrode of the LTIGBT was replaced with a trench-type electrode. The LTIGBT was designed so that the width of device was no more than 10 ${\mu}{\textrm}{m}$. The latch-up current densities were improved by 4.5 and 7.6 times, respectively, compared to those of the same sized conventional LTIGBT arid the conventional LTIGBT which has the width of 17 ${\mu}{\textrm}{m}$. The enhanced latch-up capability of the SSLTIGBT was obtained due to the fact that the hole current in the device reaches the cathode via the p+ cathode layer underneath the n+ cathode layer, directly. The forward blocking voltage of the SSLTIGBT was 125 V. At the same size, those of the conventional LTIGBT and the conventional LTIGBT with the width of 17 ${\mu}{\textrm}{m}$ were 65 V and 105 V, respectively. Because the proposed device was constructed of trench-type electrodes, the electric field In the device were crowded to trench oxide. Thus, the punch through breakdown of LTEIGBT occurred late.

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Design of a Camera Calibration System in a Smart Thermo-Sensor Based Network (스마트 열센서 네트워크의 카메라 미세조정을 위한 시스템 구축)

  • Moon Sang-Gook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2006.05a
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    • pp.924-926
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    • 2006
  • Sensor networks are an emerging area of mobile computing. Networked sensors represent a new design paradigm enabled by advances in micro electro-mechanical systems (MEMS) and low power technology. Created with integrated circuit (IC) technology and combined with computational logic, these 'smart' sensors have the benefit of small size, low cost and power consumption, and, the capability to perform on-board computation. Though this recent technological innovation has shown a significant promise in many application domains, it has also exposed several technical limitations that must be improved. In this paper, we discuss the system deploy issues for infrared thermo sensor camera calibration.

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