• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.21 no.3
• /
• pp.265-271
• /
• 2008

TCP(Tape Carrier Package), COG (Chip On Glass), COF(Chip On Film) are three methods for connecting LDI(LCD Driver IC) with LCD panels. Especially COF is growing its portion of market place because of low cost and fine pitch correspondence. But COF has a problem of the lead broken failure in LCD module process and the usage of customer. During PCB (Printed Circuit Board) bonding process, the mismatch of the coefficient of thermal expansion between PCB and D-IC makes stress-concentration in COF lead, and also D-IC bending process during module assembly process makes the level of stress in COF lead higher. As an affecting factors of lead-broken failure, the effects of SR(Solder Resister) coating on the COF lead, surface roughness and grain size of COF lead, PI(Polyimide) film thickness, lead width and the ACF(Anisotropic Conductive Film) overlap were studied, The optimization of these affecting manufacturing processes and materials were suggested and verified to prevent the lead-broken failure.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.1069-1072
• /
• 1998

Recently the development of design and automation technology and manufacturing method, has reduced the cost of chip, but it becomes more difficult to test IC chip because test technique doesn't keep up with these techniques. In case of IC testing, obtaining test vectors to be able to detect good chip or bad one is very important, but according to increasing complexity, it is very complex and difficult. Another problem is that during testing, there could be capability of physical and electrical damage on chip. Also there is difficulty in synchronization between CUT (circuit under test) and Test equipment〔1〕. Because of these difficulties, built in self test has been proposed. Not only obtaining test vectors but also reducing test time becomes hot issues nowadays. This paper presents a new test BIST(built in self test) method. Proposed BIST implementation reduces test time and obtains high fault coverage. By searching internal nodes in which are inserted test_point_cells〔2〕and allocating TPG(test pattern generation) stages, test length becomes much shorter.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.11a
• /
• pp.376-377
• /
• 2006

Chemical Mechanical Planarization (CMP) has emerged as an enabling technology for the manufacturing of multi-level metal interconnects used in high-density Integrated Circuits (IC). Recently, multi-level structures have been also widely used m the MEMS device such as micro engines, pressure sensors, micromechanical fluid pumps, micro mirrors and micro lenses. Especially, among the thin films available in IC technologies, polysilicon has probably found the widest range of uses in silicon technology based MEMS. This paper presents the characteristic of polysilicon CMP for multi-level MEMS structures. Two-step CMP process verifies that is possible to decrease dishing amount with two type of slurries characteristics. This approach is attractive because two-step CMP process can be decreased dishing amount considerably more then just one CMP process.

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.269-274
• /
• 1999

As the semiconductor industry enters the next century, we are facing to the technological changes and challenges. Optical lithography has driven by the miniaturisation of semiconductor devices and has been accompanied by an increase in wafer productivity and performance through the reduction of the IC image geometries. In the last decade, DRAM(Dynamic Random Access Memories) have been quadrupoling in level of integration every two years. Korean chip makers have been produced the memory devices, mainly DRAM, which are the driving force of IC＇s(Integrated Circuits) development and are the technology indicator for advanced manufacturing. Therefore, Korean chip makers have an important position to predict and lead the patterning technology. In this paper, we will be discussed the limitations of the optical lithography, such as KrF and ArF. And, post optical lithography technology, such as E-beam lithography, EUV and E-beam Projection Lithography shall be introduced.

• Proceedings of the KSME Conference
• /
• 2008.11a
• /
• pp.1295-1300
• /
• 2008

During the manufacturing and the service life of Au-Al wire bonded electronic packages, the ball bonds experience elevated temperatures and hence accelerated thermal diffusion reactions that promote the transformation of the Au-Al phases and the IMC growth. In this paper, the IC under high temperature storage (HTS) tests at $175^{\circ}C,\;200^{\circ}C$, and $250^{\circ}C$ are meticulously investigated. Thermal exposure resulted in the IMC growth, Kirkendall void and the crack of the Au-Al phases. The crack propagation occurs resulting in the failure of the Au-Al ball bonds. As the IC was exposed at the high temperature, decreased in the lifetime.

• Transactions of the Korean Society of Machine Tool Engineers
• /
• v.17 no.2
• /
• pp.13-22
• /
• 2008

For the accuracy correction of the micro-positioning industrial robot, micro-manipulator has been devised. The compliant mechanisms using piezoelectric actuators is necessary geometrically and structurally to be developed by the optimization approaches. The overall geometric advantage as the mechanical efficiencies of the mechanism are considered as objective functions, which respectively art the ratio of output displacement to input force, and their constraints are the vertical notion of supporting leg and the structural strength of manipulation. In optimizing the compliant mechanical amplifier, the sequential linear programming and an optimality criteria method are used for the geometrical dimensions of compliant bridges and flexure hinges. This paper presents the integrated design process which not only can maximize the mechanism feasibilities but also can ensure the positioning accuracy and sufficient workspace. Experiment and simulation are presented for validating the design process through the comparisons of the kinematical and structural performances.

• Journal of the Microelectronics and Packaging Society
• /
• v.20 no.1
• /
• pp.1-5
• /
• 2013

Wafer-to-Wafer (W2W) integration technology is an emerging technology promising many benefits, such as reduced size, improved performance, reduced power, lower cost, and divergent integration. As the maturity of W2W technology progresses, new applications will become more viable. However, at present the cost for W2W integration is still very high and both manufacturing yield and reliability issues have not been resolved yet for high volume manufacturing (HVM). Especially for WTW integration resolving compound yield issue can be a key factor for HVM. To have the full benefits of WTW integration technology more than simple wafer stacking technologies are necessary. In this paper, the manufacturing yield for W2W integration is described and the challenges of WTW integration will be discussed.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.17 no.6
• /
• pp.239-245
• /
• 2016

In this study, a 12 V PWM boost converter was designed with the optimal values of the external components of the power stage was well as the compensation stage for smart electronic applications powered by a battery device. The 12 V boost PWM converter consisted of several passive elements, such as a resistor, inductor and capacitor with a diode, power MOS switch and control IC chip for the control PWM signal. The devices of the power stage and compensation stage were designed to maintain stable operation under a range of load conditions as well as achieving the highest power efficiency. The results of this study were first verified by a simulation in SPICE from calculations of the values of major external elements comprising the converter. The design was also implemented on the prototype PCBboard using commercial IC LM3481 from Texas Instruments, which has a nominal output voltage of 12 V. The output voltage, ripple voltage, and load regulation with the line regulation were measured using a digital oscilloscope, DMM tester, and DC power supply. By configuring the converter under the same conditions as in the circuit simulation, the experimental results matched the simulation results.

• Journal of the Korean Society of Food Science and Nutrition
• /
• v.39 no.11
• /
• pp.1654-1659
• /
• 2010

In order to utilize squid liver by-products, which is normally discarded as industrial waste in the process of squid manufacturing, salt-fermented squid liver sauce was prepared experimentally and also tested for inhibitory activity against angiotensin converting enzyme (ACE). ACE inhibitory activity of squid liver sauce was increased with the elapse of fermentation days until 12 months, followed by a constant level of inhibitory activity thereafter. 15-month-old sauce ($IC_{50}=29.66\;{\mu}g$) was filtered through PM-10 membrane (M.W. cut-off 10,000 Da) to obtain the peptides fractions with ACE inhibition activity. Filtered fractions were applied to a Bio-gel P-2 column and three active fractions (A, B and C) were collected. Among them, fraction B applied to a SuperQ-Toyopearl 650S column chromatography lead to the isolation of active B-1 fraction. It has the ACE inhibitory activity ($IC_{50}=5.46\;{\mu}g$). The main composition of its amino acids is lysine, glycine and proline, which cover about 85% of the total amino acids.

• Journal of Internet Computing and Services
• /
• v.21 no.2
• /
• pp.109-119
• /
• 2020

The FPGAs are semiconductors that can be redesigned after initial fabrication. It is used in various embedded systems such as signal processing, automotive industry, defense and military systems. However, as the complexity of hardware design increases and the design and manufacturing process globalizes, there is a growing concern about hardware trojan inserted into hardware. Many detection methods have been proposed to mitigate this threat. However, existing methods are mostly targeted at IC chips, therefore it is difficult to apply to FPGAs that have different components from IC chips, and there are few detection studies targeting FPGA chips. In this paper, we propose a method to detect hardware trojan by learning the static features of hardware trojan in LUT-level netlist of FPGA using machine learning.