• Proceedings of the KIEE Conference
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• 1997.07f
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• pp.2075-2077
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• 1997

An electronic starter using MOSFET is developed to take advantage of ideal preheating and starting features which can extend the lifetime of fluorescent lamps. The preheating curcuit of the developed electronic starter is consisted of three parts - a full wave rectifier curcuit, an FET switching curcuit, and a timer curcuit for the gate switching. The curcuit allows sufficient preheating current flow before the starting to protect lamp filaments, nevertheless it shortens the Preheating time and enables a single pulse ignition at the peak level of the line voltage. Experimental results show that fluorescent lamps of 20-40W range can be initiated within rather short time of $1{\sim}1.5sec$ with preheating current of 0.6A. The electronic starter withstands more than 70.000 cycles switchings without noticeable blackening due to anode spot. These features provide Proper evidences for the advantage of direct replacement with the new starter.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.11
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• pp.56-62
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• 1999

All the cells on the whole memory array or a block of the memory array in the Flash EEPROM's are erased at the same time using Fowler-Nordheim (FN) tunneling. some of the cels are often overerased since the tunneling is not a self-limited process. In this paper, the optimum doping concentration of the floating gate solve the overerase problem has been studied. For these studies, N-type MOSFETs and MOS capacitors with various doping concentrations of the gate polysilicon have been fabricated and their electrical characteristics have been measured and analyzed. As the results of the experiment, it has been found that the overerase problem can be prevented if the doping concentration of the floating gate is low enough (i.e. below $1.3{\times}10^{18}/cm^3$). It is because the potential difference between the floating gate and the source is lowered due to the formation of the depletion layer in the floating gate and thus the erasing operation stops by itself after most of the electrons stored in the floating gate are extracted. On the other hand, the uniformity of the Vt and the gm has been significantly poor if the coping concentration of the floating, gate is too much lowered (i.e. below $1.3{\times}10^{17}/cm^3$), which is believed to be due to nonuniform loss of the dopants from the nonuniform segregation in the floating gate. Consequently, the optimum doping concentration of the floating gate to suppress the overerase problem and get the uniform Vt and has been found to range from $1.3{\times}10^{17}/cm^3$ to $1.3{\times}10^{18}/cm^3$ in the Flash EEPROM.

• Transactions on Electrical and Electronic Materials
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• v.7 no.1
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• pp.1-6
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• 2006

Hot carrier degradation and roll off characteristics of threshold voltage ($V_{t1}$) on NMOSFETs as I/O transistor are studied as a function of Lightly Doped Drain (LDD) structures. Pocket dose and the combination of Phosphorus (P) and Arsenic (As) dose are applied to control $V_{t1}$ roll off down to the $10\%$ gate length margin. It was seen that the relationship between $V_{t1}$ roll off characteristic and substrate current depends on P dopant dose. For the first time, we found that the n-p-n transistor triggering voltage ($V_{t1}$) depends on drain current, and both $I_{t2}$ and snapback holding voltage ($V_{sp}$) depend on the substrate current by characterization with a transmission line pulse generator. Also it was found that the improved lifetime for hot carrier stress could be obtained by controlling the P dose as loosing the $V_{t1}$ roll off margin. This study suggests that the trade-off characteristic between gate length margin and channel hot carrier (CHC) lifetime in NMOSFETs should be determined by considering Electrostatic Discharge (ESD) characteristic.

• Journal of Sensor Science and Technology
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• v.12 no.4
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• pp.149-155
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• 2003

A PMOSFET photodetector for highly-sensitive active pixel sensor(APS) is presented. This sensor uses 5V power supply and has been designed and fabricated using I-poly and 2-metal $1.5{\mu}m$ CMOS technology. The feature of a PMOSFET photodetector is that the polysilicon gate of the PMOSFET was connected to n-well, in order to increase the photo sensitivity. The designed MOS photodetector has similar $I_{DS}-V_{DS}$ characteristics with a standard MOSFET. One dimensional image sensor with 16 pixels based on the PMOSFET photodetector has also been designed and fabricated. Unit pixel of the designed sensor consists of a PMOSFET photodetector and 4 NMOSFETs. Unit pixel area is $86{\mu}m{\times}90.5{\mu}m$ and its fill factor is about 12%.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.123-129
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• 1996

LDD structure is widely accepted in fabricating short channel MOSFETs due to reduced short channel effect originated form lower drain edge electric field. However, modeling of the LDD device is troublesome because the analysis methods of LDD region known are either too complicated or inaccurate. To solve the problem, this paper presents a nonlinear resistance model for the LDD region based on teh fact that the electron mobility changes with positive gate bias because accumulation layer of electrons is formed at the surface of the LDD region. To prove the usefulness of the model, single source/drain and LDD nMOSFETs were fabricated with 0.35$\mu$m CMOS technolgoy. For the fabricated devices we have measured I$_{ds}$-V$_{gs}$ characteristics and compare them to the modeling resutls. First of all, we calculated channel and LDD region mobility from I$_{ds}$-V$_{gs}$ characteristics of 1050$\AA$ sidewall, 5$\mu$m channel length LDD NMOSFET. Then we MOSFET and found good agreement with experiments. Next, we use calculated channel and LDD region mobility to model I$_{ds}$-V$_{gs}$ characteristics of LDD mMOSFET with 1400 and 1750$\AA$ sidewall and 5$\mu$m channel length and obtained good agreement with experiment. The single source/drain device characteristic modeling results indicates that the cahnnel mobility obtained form our model in LDD device is accurate. In the meantime, we found that the LDD region mobility is governed by phonon and surface roughness scattering from electric field dependence of the mobility. The proposed model is useful in device and circuit simulation because it can model LDD device successfully even though it is mathematically simple.

• Journal of Satellite, Information and Communications
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• v.10 no.4
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• pp.1-5
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• 2015

The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different partial p-well(PPW) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device shows typical SCR-like characteristics with low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW_PGM(primary gate middle) and optimal CPS(counter pocket source) implant demonstrate the stable ESD protection performance with high latch-up immunity.

• Journal of the Korean Vacuum Society
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• v.17 no.3
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• pp.199-203
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• 2008

The effects of surface treatment by $O_2$ plasma on the Bio-FETs were investigated by using the pseudo-MOSFETs on the SOI substrates. After a surface treatment by $O_2$ plasma with different RF powers, the current-voltage and field effect mobility of pseudo-MOSFETs were measured by applying back gate bias. The subthreshold characteristics of pseudo-MOSFETs were significantly degraded with increase of RF power. Additionally, a forming gas anneal process in 2 % diluted $H_2/N_2$ ambient was developed to recover the plasma process induced surface damages. A considerable improvement of the subthreshold characteristics was achieved by the forming gas anneal. Therefore, it is concluded that the pseudo-MOSFETs are a powerful tool for monitoring the surface treatment of Bio-FETs and the forming gas anneal process is effective for improving the electrical characteristics of Bio-FETs.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.259-259
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• 2016

반도체 산업 전반에 걸쳐 이루어지고 있는 연구는 소자를 더 작게 만들면서도 구동능력은 우수한 소자를 만들어내는 것이라고 할 수 있다. 따라서 소자의 미세화와 함께 트랜지스터의 구동능력의 향상을 위한 기술개발에 대한 필요성이 점차 커지고 있으며, 고유전(high-k)재료를 트랜지스터의 게이트 절연막으로 이용하는 방법이 개발되고 있다. High-k 재료를 트랜지스터의 게이트 절연막에 적용하면 낮은 전압으로 소자를 구동할 수 있어서 소비전력이 감소하고 소자의 미세화 측면에서도 매우 유리하다. 그러나, 초미세화된 소자를 제작하기 위하여 high-k 절연막의 두께를 줄이게 되면, 전기적 용량(capacitance)은 커지지만 에너지 밴드 오프셋(band-offset)이 기존의 실리콘 산화막(SiO2)보다 작고 또한 열공정에 의해 쉽게 결정화가 이루어지기 때문에 누설전류가 발생하여 소자의 열화를 초래할 수 있다. 따라서, 최근에는 이러한 문제를 해결하기 위하여 게이트 절연막 엔지니어링을 통해서 누설전류를 줄이면서 전기적 용량을 확보할 수 있는 연구가 주목받고 있다. 본 실험에서는 high-k 물질인 Ta2O5와 SiO2를 적층시켜서 누설전류를 줄이면서 동시에 높은 캐패시턴스를 달성할 수 있는 게이트 절연막 엔지니어링에 대한 연구를 진행하였다. 먼저 n-type Si 기판을 표준 RCA 세정한 다음, RF sputter를 사용하여 두께가 Ta2O5/SiO2 = 50/0, 50/5, 50/10, 25/10, 25/5 nm인 적층구조의 게이트 절연막을 형성하였다. 다음으로 Al 게이트 전극을 150 nm의 두께로 증착한 다음, 전기적 특성 개선을 위하여 furnace N2 분위기에서 $400^{\circ}C$로 30분간 후속 열처리를 진행하여 MOS capacitor 소자를 제작하였고, I-V 및 C-V 측정을 통하여 형성된 게이트 절연막의 전기적 특성을 평가하였다. 그 결과, Ta2O5/SiO2 = 50/0, 50/5, 50/10 nm인 게이트 절연막들은 누설전류는 낮지만, 큰 용량을 얻을 수 없었다. 한편, Ta2O5/SiO2 = 25/10, 25/5 nm의 조합에서는 충분한 용량을 확보할 수 있었다. 적층된 게이트 절연막의 유전상수는 25/5 nm, 25/10 nm 각각 8.3, 7.6으로 비슷하였지만, 문턱치 전압(VTH)은 각각 -0.64 V, -0.18 V로 25/10 nm가 0 V에 보다 근접한 값을 나타내었다. 한편, 누설전류는 25/10 nm가 25/5 nm보다 약 20 nA (@5 V) 낮은 것을 확인할 수 있었으며 절연파괴전압(breakdown voltage)도 증가한 것을 확인하였다. 결론적으로 Ta2O5/SiO2 적층 절연막의 두께가 25nm/10nm에서 최적의 특성을 얻을 수 있었으며, 본 실험과 같이 게이트 절연막 엔지니어링을 통하여 효과적으로 누설전류를 줄이고 게이트 용량을 증가시킴으로써 고집적화된 소자의 제작에 유용한 기술로 기대된다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.1
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• pp.101-105
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• 2024

4H-SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed to achieve lower specific-on-resistance (R_on,sp), and the gate oxides have been thermally grown. The poor channel mobility resulting from the high interface trap density (D_it) at the SiO₂/4H-SiC interface significantly affects the higher switching loss of the power device. Therefore, the development of novel fabrication processes to enhance the quality of the SiO₂/4H-SiC interface is required. In this paper, NO post-oxidation annealing (POA) by using the conditions of N₂ diluted NO at a high temperature (1,300℃) is proposed to reduce the high interface trap density resulting from thermal oxidation. The NO POA is carried out in various NO ambient (0, 10, 50, and 100% NO mixed with 100, 90, 50, and 0% of high purity N₂ gas to achieve the optimized condition while maintaining a high temperature (1,300℃). To confirm the optimized condition of the NO POA, measuring capacitance-voltage (C-V) and current-voltage (I-V), and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) are employed. It is confirmed that the POA condition of 50% NO at 1,300℃ facilitates the equilibrium state of both the oxidation and nitridation at the SiO₂/4H-SiC interface, thereby reducing the D_it.