• The Korean Journal of Physiology and Pharmacology
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• v.9 no.3
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• pp.179-186
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• 2005

Whole bee venom (WBV) and its major component, melittin, have been reported to induce long-lasting spontaneous flinchings and hyperalgesia. The current study was designed to elucidate the peripheral and spinal mechanisms of N-methyl-D-aspartate (NMDA) and non-NMDA receptors by which intraplantar (i.pl.) injection of WBV and melittin induced nociceptive responses. Changes in mechanical threshold and flinching behaviors were measured after the injection of WBV (0.04 mg or 0.1 mg/paw) and melittin (0.02 mg or 0.05 mg/paw) into the mid-plantar area of a rat hindpaw. MK-801 and CNQX (6-cyano-7-nitroquinoxaline-2,3-dione disodium) were administered intrathecally (i.t. $10{\mu}g$) or i.pl.($15{\mu}g$) 15 min before or i.t. 60 min after i.pl. WBV and melittin injection. Intrathecal pre- and postadministration of MK-801 and CNQX significantly attenuated the ability of high dose WBV and melittin to reduce paw withdrawal threshold (PWT). In the rat injected with low dose, but not high dose, of WBV and melittin, i.pl. injection of MK-801 effectively suppressed the decrease of PWTs only at the later time-points, but the inhibitory effect of CNQX (i.pl.) was significant at all time-point after the injection of low dose melittin. High dose WBV- and melittin-induced spontaneous flinchings were significantly suppressed by i.t. administration of MK-801 and CNQX, and low dose WBV- and melittin-induced flinchings were significantly reduced only by intraplantarly administered CNQX, but not by MK-801. These experimental flinchings suggest that spinal, and partial peripheral mechanisms of NMDA and non-NMDA receptors are involved in the development and maintenance of WBV- and melittin-induced nociceptive responses.

• Korean Journal of Materials Research
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• v.7 no.3
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• pp.213-217
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• 1997

AOhf(Hcousto-r)l)tic niodulator) with :!OOlIiz freclucncl- and Sfi(;(Seconrl harmonic generation) green lasel-Lvith 53% nm wavelength were used for Il\'IIII~Dii.it,ii v~ilco disk recorder) FOI rhe appli~aptin of high densit]. optical recording, a high po\ver I ~ c r is r c ~ ~ l i ~ i l - u l ic I !tic. s\-sti,m a n d optic.,~I io;iting l,t)c>rs of each optical device must have a high laser damage threshoid hie rn;itie ant] retlwtive coatings on a $TeO_{2}$ singlc crystal. which is used as an acoustooptic material, by E-beam evaporation method. Laser damage threshold \vas nicdsureci hy Ar laser with the input power oi 0.55LV 1,aser damage threiholti 01 $ZrO_{2}$ and $SiO_{2}$. filn-is were higher than $AI_{2}O_{3}$ f i l m U'e also investigated a long--tern1 stability of the output po\ver of St{(; green laser

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.4
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• pp.258-264
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• 2004

This paper propose a method that GOP structure based on the picture complexity change realtime adaptive without pre-analysis or time delay. Proposed algorithm calculates the complexity of pictures at first, and the ratio of the complexity( X$\sub$p/ /X$\sub$i/) between P picture and I picture is calculated. The suitable M value for the three picture select by comparing with predetermined threshold. Used bit and vbv_delay the value of GOP is calculated according to selected M. Experimental results show that the prediction error is reduce than the fixed GOP structure. Since the complexity distribution of the sequence is different, applied limits of threshold value is changed, also.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.835-838
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• 1998

본 연구에서는 칼라 CCD 센서를 제어하여, shading과 .gamma. correction 된 데이터를 읽어 들여, 이를 이진레벨 데이터로 바꾼후, 원래의 다치레벨 또는 이진레벨 데이터를 SCSI나 DMA I/F를 통해 전달하는 ASIC을 설계하였다. 본 ASIC에서는 이진화를 위하여 문자 모드에서는 simple threshold와 LAT(local adaptive threshold) 알고리즘을, 그림모드에서는 stucki error diffusion 알고리즘을 적용하였다. 그리고, 구성은 CCD센서 제어블락, 스텝 모타 제어제어블락, 이미지 축소블락, 데이터 이진화 블락, 그리고 DATA I/F 블락 등으로 이루어져 있다. 또한 사용된 technology는 삼성 0.5um CMOS standard cell이며, 크기는 45K gates(내부 메모리 제외)이고, 160QFP package로 구현되었다. ㅎㅁㅅㄷㄴ (soqn apa

• Journal of the Korean Institute of Telematics and Electronics
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• v.5 no.2
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• pp.8-14
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• 1968

A linear current-pulse discriminator consisting: of a transistor monostable multivibrator and a Si tunnel diode is described. The input currant pulse range is about 50$\mu$A~5.23mA. The measured maximum linearity deviation is $\pm$0.75% in the input current pulse range mentioned above. The pulse resolving ability of the discriminator measured depends upon the bias current through the T, D. ; and, under the reverse bias current of 3mA, the resolving time is 2rs if allow the excess pulse amplitude of 5%. The threshold stability of the discriminator depends mainly upon the stability of the peak current Ip of the T. D. ; and, under the ambient temperature variation from $0^{\circ}C$ to 5$0^{\circ}C$, no bigger threshold variation than the maximum linearity deviation, i. e. $\pm$ 0.75%, was observed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.69-75
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• 2003

Cell transistor and data retention time characteristics were studied in 90 nm design rule 512M-bit DRAM, for the first time. And, the characteristics of cell transistor are investigated for different STI gap-fill materials. HDP oxide with high compressive stress increases the threshold voltage of cell transistor, whereas the P-SOG oxide with small stress decreases the threshold voltage of cell transistor. Stress between silicon and gap-fill oxide material is found to be the major cause of the shift of the cell transistor threshold voltage. If high stress material is used for STI gap fill, channel-doping concentration can be reduced, so that cell junction leakage current is decreased and data retention time is increased.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.3
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• pp.146-151
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• 2018

In this study, we compared the threshold-voltage extraction methods of accumulation-type JLDG (junctionless double-gate) MOSFETs (metal-oxide semiconductor field-effect transistors). Threshold voltage is the most basic element of transistor design; therefore, accurate threshold-voltage extraction is the most important factor in integrated-circuit design. For this purpose, analytical potential distributions were obtained and diffusion-drift current equations for these potential distributions were used. There are the ${\phi}_{min}$ method, based on the physical concept; the linear extrapolation method; and the second and third derivative method from the $I_d-V_g$ relation. We observed that the threshold-voltages extracted using the maximum value of TD (third derivatives) and the ${\phi}_{min}$ method were the most reasonable in JLDG MOSFETs. In the case of 20 nm channel length or more, similar results were obtained for other methods, except for the linear extrapolation method. However, when the channel length is below 20 nm, only the ${\phi}_{min}$ method and the TD method reflected the short-channel effect.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.48-52
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• 1998

We fabricated the newly proposed nano structure memory with SOI edge channel and a nano dot. The width of the edge channel of this device, which uses the side wall as a channel and has a nano dot on this channel region, was determined by the thickness of the recessed top-silicon layer of SOI wafer. The size of side-wall nano dot was determined by the RIE etch and E-Beam lithography. The I$_{d}$-V$_{d}$, I$_{d}$-V$_{g}$ characteristics of the devices without nano dots and memory characteristics of the devices with nano dots were obtained, where the voltage scan was done between -20 V and 14 V and the threshold voltage shift was about 1 V.t 1 V.

• Journal of the Korean Institute of Telematics and Electronics
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• v.16 no.4
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• pp.36-46
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• 1979

Using N_ Ch silicon gate technology . the capacitors and transistors with various dimenssion were fabricated. Although the applied process was somewhat standard the conditions of ion implantation for the gate were varied by changing the implant energies from 30keV to 60keV for B and from 100 keV to 175keV for P . The doses of the implant also changed from 3 $\times$ 10 /$\textrm{cm}^2$ to 5 $\times$ 10 /$\textrm{cm}^2$ for B and from 4$\times$ 10 /$\textrm{cm}^2$ to 7 $\times$ 10 /$\textrm{cm}^2$ for P . The D. C. parameters such as threshold voltage. substrate doping level, the degree of inversion, capacitance. flat band voltage, depletion layer width, gate oxide thickless, surface states, motile charge density, electron mobility. leakage current were evaluated and also compared with the corresponing theoretical values and / or good numbers for application. The threshold voltages measured using curve tracer and C-V plot gave good agreements with the values calculated from SUPREM II which has been developed by Stanford University process group. The threshold vol tapes with back gate bias were used to calculate the change of the substrate doping level. The measured subthreshold slope enabled the prediction of the degree of inversion The D. C. testing results suggest the realized capacitors and transistors are suited for the memory applications.

• The Journal of the Acoustical Society of Korea
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• v.19 no.3
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• pp.20-25
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• 2000

This paper proposes the method of surface classification and threshold value selection for surface classification of the three-dimensional object recognition. The processings of three-dimensional image processing system consist of three steps, i.e, acquisition of range data, feature extraction and matching process. This paper proposes the method of shape feature extraction from the acquired rage data in the entire three-dimensional image processing system. In order to achieve these goals, firstly, this article proposes the surface classification method by using the distribution characteristics of sign value from range values. Also pre-existing method which uses the K-curvature and K-curvature has limitation in the practical threshold value selection. To overcome this, this article proposes the selection of threshold value for surface classification. Finally, the effectiveness of this article is demonstrated by the several experiments.