• Journal of IKEEE
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• v.15 no.3
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• pp.205-210
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• 2011

A novel hysteresis tunable monolithic comparator circuit based on a 0.35 ${\mu}m$ CMOS process is suggested in this paper. To tune the threshold voltage of the hysteresis in the comparator circuit, two external digital bits are used with supply voltage of 3.3V. The threshold voltage of the suggested comparator circuit is controlled by 234mV by change of 4 digital control bits in the simulation, which is a close agreement to the analytic calculation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.598-601
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• 2003

Most of all, DTC drive is very simple in its implementation because it needs only two hysteresis comparator and switching vector table for both flux and torque control. The switching strategy of a conventional direct torque control scheme which is based on hysteresis comparator results in a variable switching frequency which depends on the speed, flux, stator voltage and the hysteresis of the comparator. The amplitude of hysteresis band greatly influences on the drive performance such as flux and torque ripple and inverter switching frequency. In this paper the influence of the amplitudes of flux and torque hysteresis bands and sampling time of control program on the torque and flux ripples are investigated. Simulation results confirm the superiority of the DTC under the proposed method over the conventional DTC.

• Journal of IKEEE
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• v.16 no.1
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• pp.20-27
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• 2012

In order to overcome jamming, a hysteresis tunable monolithic comparator circuit based on a 0.35 ${\mu}m$ CMOS process is suggested, designed, fabricated, measured and analyzed in this paper. To tune the threshold voltage of the hysteresis in the comparator circuit, two external digital bits are used with supply voltage of 3.3V. An improved variable hysteresis comparator circuit controlled by serial digital bits is suggested, designed and simulated to overcome jamming in modern warfare.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.812-815
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• 2003

Most of all, DTC drive is very simple in its implementation because it needs only two hysteresis comparator and switching vector table for both flux and torque control. The switching strategy of a conventional direct torque control scheme which is based on hysteresis comparator results in a variable switching frequency which depends on the speed, flux, stator voltage and the hysteresis of the comparator. The amplitude of hysteresis band greatly influences on the drive performance such as flux and torque ripple and inverter switching frequency. In this paper the influence of the amplitudes of flux and torque hysteresis bands and sampling time of control program on the torque and flux ripples are investigated. Simulation results confirm the superiority of the DTC under the proposed method over the conventional DTC.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.1035-1037
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• 2001

This paper presents an improved hys- teresis current control method for three-phase PWM power inverters using 3-level comparator. Hysteresis current controller using 3-level comparator has an advantage of constant switching frequency compared with conventional hysteresis current controller. However, this method has disadvantage that the longer sampling period, the larger current error because the switching is performed without considering current error magnitude of each phase. The proposed method improves the control performance by selecting the optimum switching pattern in which the magnitudes of current errors are considered introducing space vector concept. Simulation results using Matlab/Simulink show that the proposed control method reduces current error keeping the merit of previous hysteresis current control method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.37-42
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• 2010

A novel hysteresis tunable monolithic comparator circuit based on a $0.35{\mu}m$ CMOS process is suggested, designed, fabricated, measured and analyzed in this paper. To tune the threshold voltage of the hysteresis in the comparator circuit, two external digital bits are used with supply voltage of 3.3V.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.291-296
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• 2015

This paper describes the design of a high-speed comparator for high-speed automatic test equipment (ATE). The normal comparator block, which compares the detected signal from the device under test (DUT) to the reference signal from an internal digital-to-analog converter (DAC), is composed of a rail-to-rail first pre-amplifier, a hysteresis amplifier, and a third pre-amplifier and latch for high-speed operation. The proposed continuous comparator handles high-frequency signals up to 800MHz and a wide range of input signals (0~5V). Also, to compare the differences of both common signals and differential signals between two DUTs, the proposed differential mode comparator exploits one differential difference amplifier (DDA) as a pre-amplifier in the comparator, while a conventional differential comparator uses three op-amps as a pre-amplifier. The chip was implemented with $0.18{\mu}m$ Bipolar CMOS DEMOS (BCDMOS) technology, can compare signal differences of 5mV, and operates in a frequency range up to 800MHz. The chip area is $0.514mm^2$.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.3
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• pp.1-7
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• 2014

This paper describes the implementation of high speed comparator for the ATE (automatic test equipment) system. The comparator block is composed of continuous comparator, differential difference amplifier(DDA) and output stage. For the wide input dynamic range of 0V to 5V, and for the high speed operation (1~800MHz), high speed rail-to-rail amplifier is used in the first stage. And hysteresis circuits, pre-amp and latch are followed for high speed operation. To measure the difference of output signals between the two devices under test (DUTs), a DDA is applied because it can detect the differences of both common signals and differential signals. This comparator chip was implemented with $0.18{\mu}m$ BCDMOS process and can compare the signal difference of 5mV up to the frequency range of 800 MHz. The chip area of the comparator is $620{\mu}m{\times}830{\mu}m$.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.1152-1154
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• 2002

In this paper, a direct torque control method of an induction motor is proposed which enables constant switching frequency. The switching strategy of a conventional direct torque control scheme which is based on hysteresis comparator results in a variable switching frequency which depends on the speed, flux, stator voltage and hysteresis band of the comparator. This paper proposes a new switching strategy which determine the effective switching time on each switching period by comparing the ascending and descending torque slopes. The simulation results are presented to verify this proposed scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.9
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• pp.753-763
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• 1990

This paper proposes a new current control strategy for current regulated VSI-PWM lnverter. The conventional hysteresis control method has good dynamic response, but the switching frequency in lower region are high because it does not optimise switching patterns. Proposed current control strategy can optimize switching patterns. As regulater, three level comparator are used, the output of comparator select appropriate inverter output voltage vectors via switching table stored in EPROM. The simulation and experimental results in comparison to conventional hysteresis strategy are presented and discussed.